2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
24 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
26 #define MXC_CCM_BASE CCM_BASE_ADDR
28 /* DPLL register mapping structure */
44 /* Register maping of CCM*/
50 u32 cacrr; /* 0x0010*/
54 u32 cscmr2; /* 0x0020 */
58 u32 cdcdr; /* 0x0030 */
62 u32 cscdr4; /* 0x0040 */
66 u32 ctor; /* 0x0050 */
70 u32 ccosr; /* 0x0060 */
74 u32 CCGR2; /* 0x0070 */
78 u32 CCGR6; /* 0x0080 */
80 u32 CCGR7; /* 0x0084 */
85 /* Define the bits in register CCR */
86 #define MXC_CCM_CCR_COSC_EN (0x1 << 12)
87 #if defined(CONFIG_MX51)
88 #define MXC_CCM_CCR_FPM_MULT (0x1 << 11)
90 #define MXC_CCM_CCR_CAMP2_EN (0x1 << 10)
91 #define MXC_CCM_CCR_CAMP1_EN (0x1 << 9)
92 #if defined(CONFIG_MX51)
93 #define MXC_CCM_CCR_FPM_EN (0x1 << 8)
95 #define MXC_CCM_CCR_OSCNT_OFFSET 0
96 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
97 #define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF)
98 #define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF)
100 /* Define the bits in register CCSR */
101 #if defined(CONFIG_MX51)
102 #define MXC_CCM_CCSR_LP_APM (0x1 << 9)
103 #elif defined(CONFIG_MX53)
104 #define MXC_CCM_CCSR_LP_APM (0x1 << 10)
105 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9)
107 #define MXC_CCM_CCSR_STEP_SEL_OFFSET 7
108 #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
109 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7)
110 #define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3)
111 #define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5
112 #define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5)
113 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5)
114 #define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3)
115 #define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3
116 #define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3)
117 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3)
118 #define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3)
119 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2)
120 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1)
121 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1
123 /* Define the bits in register CACRR */
124 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
125 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
126 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7)
127 #define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7)
129 /* Define the bits in register CBCDR */
130 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30)
131 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27
132 #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
133 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27)
134 #define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7)
135 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
136 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
137 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
138 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
139 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22)
140 #define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7)
141 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
142 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
143 #define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19)
144 #define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7)
145 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
146 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
147 #define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16)
148 #define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7)
149 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
150 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
151 #define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13)
152 #define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7)
153 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
154 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
155 #define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10)
156 #define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7)
157 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
158 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
159 #define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8)
160 #define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3)
161 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
162 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
163 #define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6)
164 #define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3)
165 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
166 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
167 #define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3)
168 #define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7)
169 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
170 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
171 #define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7)
172 #define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7)
174 /* Define the bits in register CSCMR1 */
175 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
176 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
177 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30)
178 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3)
179 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
180 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
181 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28)
182 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3)
183 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
184 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
185 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
186 #define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24)
187 #define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3)
188 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
189 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
190 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22)
191 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3)
192 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
193 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
194 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20)
195 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3)
196 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
197 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
198 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
199 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
200 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16)
201 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3)
202 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
203 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
204 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14)
205 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
206 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
207 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
208 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12)
209 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
210 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
211 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
212 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
213 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
214 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8)
215 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
216 #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
217 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
218 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
219 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
220 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4)
221 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
222 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
223 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
224 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2)
225 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3)
226 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
227 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
229 /* Define the bits in register CSCDR2 */
230 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
231 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
232 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25)
233 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7)
234 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
235 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
236 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19)
237 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F)
238 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
239 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
240 #define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16)
241 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
242 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
243 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
244 #define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9)
245 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F)
246 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
247 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6)
248 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6)
249 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7)
250 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0
251 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F
252 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F)
253 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F)
255 /* Define the bits in register CBCMR */
256 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
257 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
258 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14)
259 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
260 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
261 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
262 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12)
263 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
264 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
265 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
266 #define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10)
267 #define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3)
268 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
269 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
270 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8)
271 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
272 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
273 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
274 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6)
275 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3)
276 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
277 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
278 #define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4)
279 #define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
280 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
281 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
283 /* Define the bits in register CSCDR1 */
284 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
285 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
286 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22)
287 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7)
288 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
289 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
290 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19)
291 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7)
292 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
293 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
294 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16)
295 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
296 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
297 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
298 #define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14)
299 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3)
300 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
301 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
302 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11)
303 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7)
304 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
305 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
306 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8)
307 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7)
308 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
309 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
310 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6)
311 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3)
312 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
313 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
314 #define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3)
315 #define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7)
316 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
317 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
318 #define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7)
319 #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7)
321 /* Define the bits in register CCDR */
322 #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
324 /* Define the bits in register CCGRx */
325 #define MXC_CCM_CCGR_CG_MASK 0x3
326 #define MXC_CCM_CCGR_CG_OFF 0x0
327 #define MXC_CCM_CCGR_CG_RUN_ON 0x1
328 #define MXC_CCM_CCGR_CG_ON 0x3
330 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0
331 #define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0)
332 #define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2
333 #define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2)
334 #define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4
335 #define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4)
336 #define MXC_CCM_CCGR0_TZIC_OFFSET 6
337 #define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6)
338 #define MXC_CCM_CCGR0_DAP_OFFSET 8
339 #define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8)
340 #define MXC_CCM_CCGR0_TPIU_OFFSET 10
341 #define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10)
342 #define MXC_CCM_CCGR0_CTI2_OFFSET 12
343 #define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12)
344 #define MXC_CCM_CCGR0_CTI3_OFFSET 14
345 #define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14)
346 #define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16
347 #define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16)
348 #define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18
349 #define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18)
350 #define MXC_CCM_CCGR0_ROMCP_OFFSET 20
351 #define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20)
352 #define MXC_CCM_CCGR0_ROM_OFFSET 22
353 #define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22)
354 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24
355 #define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24)
356 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26
357 #define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26)
358 #define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28
359 #define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28)
360 #define MXC_CCM_CCGR0_IIM_OFFSET 30
361 #define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30)
363 #define MXC_CCM_CCGR1_TMAX1_OFFSET 0
364 #define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0)
365 #define MXC_CCM_CCGR1_TMAX2_OFFSET 2
366 #define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2)
367 #define MXC_CCM_CCGR1_TMAX3_OFFSET 4
368 #define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4)
369 #define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6
370 #define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6)
371 #define MXC_CCM_CCGR1_UART1_PER_OFFSET 8
372 #define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8)
373 #define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10
374 #define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10)
375 #define MXC_CCM_CCGR1_UART2_PER_OFFSET 12
376 #define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12)
377 #define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14
378 #define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14)
379 #define MXC_CCM_CCGR1_UART3_PER_OFFSET 16
380 #define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16)
381 #define MXC_CCM_CCGR1_I2C1_OFFSET 18
382 #define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18)
383 #define MXC_CCM_CCGR1_I2C2_OFFSET 20
384 #define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20)
385 #if defined(CONFIG_MX51)
386 #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22
387 #define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22)
388 #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24
389 #define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24)
390 #elif defined(CONFIG_MX53)
391 #define MXC_CCM_CCGR1_I2C3_OFFSET 22
392 #define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22)
394 #define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26
395 #define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26)
396 #define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28
397 #define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28)
398 #define MXC_CCM_CCGR1_SCC_OFFSET 30
399 #define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30)
401 #if defined(CONFIG_MX51)
402 #define MXC_CCM_CCGR2_USB_PHY_OFFSET 0
403 #define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0)
405 #define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2
406 #define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2)
407 #define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4
408 #define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4)
409 #define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6
410 #define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6)
411 #define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8
412 #define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8)
413 #define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10
414 #define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10)
415 #define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12
416 #define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12)
417 #define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14
418 #define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14)
419 #define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16
420 #define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16)
421 #define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18
422 #define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18)
423 #define MXC_CCM_CCGR2_GPT_HF_OFFSET 20
424 #define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20)
425 #define MXC_CCM_CCGR2_OWIRE_OFFSET 22
426 #define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22)
427 #define MXC_CCM_CCGR2_FEC_OFFSET 24
428 #define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24)
429 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26
430 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26)
431 #define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28
432 #define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28)
433 #define MXC_CCM_CCGR2_TVE_OFFSET 30
434 #define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30)
436 #define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0
437 #define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0)
438 #define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2
439 #define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2)
440 #define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4
441 #define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4)
442 #define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6
443 #define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6)
444 #define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8
445 #define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8)
446 #define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10
447 #define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10)
448 #define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12
449 #define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12)
450 #define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14
451 #define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14)
452 #define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16
453 #define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16)
454 #define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18
455 #define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18)
456 #define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20
457 #define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20)
458 #define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22
459 #define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22)
460 #define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24
461 #define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24)
462 #define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26
463 #define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26)
464 #define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28
465 #define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28)
466 #define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30
467 #define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30)
469 #define MXC_CCM_CCGR4_PATA_OFFSET 0
470 #define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0)
471 #if defined(CONFIG_MX51)
472 #define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2
473 #define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2)
474 #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4
475 #define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4)
476 #elif defined(CONFIG_MX53)
477 #define MXC_CCM_CCGR4_SATA_OFFSET 2
478 #define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2)
479 #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6
480 #define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6)
481 #define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8
482 #define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8)
483 #define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10
484 #define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10)
485 #define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12
486 #define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12)
488 #define MXC_CCM_CCGR4_SAHARA_OFFSET 14
489 #define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14)
490 #define MXC_CCM_CCGR4_RTIC_OFFSET 16
491 #define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16)
492 #define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18
493 #define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18)
494 #define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20
495 #define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20)
496 #define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22
497 #define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22)
498 #define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24
499 #define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24)
500 #define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26
501 #define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26)
502 #define MXC_CCM_CCGR4_SRTC_OFFSET 28
503 #define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28)
504 #define MXC_CCM_CCGR4_SDMA_OFFSET 30
505 #define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30)
507 #define MXC_CCM_CCGR5_SPBA_OFFSET 0
508 #define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0)
509 #define MXC_CCM_CCGR5_GPU_OFFSET 2
510 #define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2)
511 #define MXC_CCM_CCGR5_GARB_OFFSET 4
512 #define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4)
513 #define MXC_CCM_CCGR5_VPU_OFFSET 6
514 #define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6)
515 #define MXC_CCM_CCGR5_VPU_REF_OFFSET 8
516 #define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8)
517 #define MXC_CCM_CCGR5_IPU_OFFSET 10
518 #define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10)
519 #if defined(CONFIG_MX51)
520 #define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12
521 #define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12)
522 #elif defined(CONFIG_MX53)
523 #define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12
524 #define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12)
526 #define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14
527 #define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14)
528 #define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16
529 #define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16)
530 #define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18
531 #define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18)
532 #define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20
533 #define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20)
534 #define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22
535 #define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22)
536 #define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24
537 #define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24)
538 #define MXC_CCM_CCGR5_SPDIF0_OFFSET 26
539 #define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26)
540 #if defined(CONFIG_MX51)
541 #define MXC_CCM_CCGR5_SPDIF1_OFFSET 28
542 #define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28)
544 #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30
545 #define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30)
547 #if defined(CONFIG_MX53)
548 #define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0
549 #define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0)
550 #define MXC_CCM_CCGR6_OCRAM_OFFSET 2
551 #define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2)
553 #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4
554 #define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4)
555 #if defined(CONFIG_MX51)
556 #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6
557 #define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6)
558 #define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8
559 #define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8)
560 #elif defined(CONFIG_MX53)
561 #define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8
562 #define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8)
564 #define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10
565 #define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10)
566 #define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12
567 #define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12)
568 #define MXC_CCM_CCGR6_GPU2D_OFFSET 14
569 #define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14)
570 #if defined(CONFIG_MX53)
571 #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16
572 #define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16)
573 #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18
574 #define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18)
575 #define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20
576 #define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20)
577 #define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22
578 #define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22)
579 #define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24
580 #define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24)
581 #define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26
582 #define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26)
583 #define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28
584 #define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28)
585 #define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30
586 #define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30)
588 #define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0
589 #define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0)
590 #define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2
591 #define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2)
592 #define MXC_CCM_CCGR7_MLB_OFFSET 4
593 #define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4)
594 #define MXC_CCM_CCGR7_IEEE1588_OFFSET 6
595 #define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6)
596 #define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8
597 #define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8)
598 #define MXC_CCM_CCGR7_UART4_PER_OFFSET 10
599 #define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10)
600 #define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12
601 #define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12)
602 #define MXC_CCM_CCGR7_UART5_PER_OFFSET 14
603 #define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14)
606 /* Define the bits in register CLPCR */
607 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
609 #define MXC_DPLLC_CTL_HFSM (1 << 7)
610 #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
612 #define MXC_DPLLC_OP_PDF_MASK 0xf
613 #define MXC_DPLLC_OP_MFI_OFFSET 4
614 #define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
615 #define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4)
616 #define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf)
618 #define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff
620 #define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff
622 #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */