2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
24 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
26 #define MXC_CCM_BASE CCM_BASE_ADDR
28 /* DPLL register mapping structure */
44 /* Register maping of CCM*/
50 u32 cacrr; /* 0x0010*/
54 u32 cscmr2; /* 0x0020 */
58 u32 cdcdr; /* 0x0030 */
62 u32 cscdr4; /* 0x0040 */
66 u32 ctor; /* 0x0050 */
70 u32 ccosr; /* 0x0060 */
74 u32 CCGR2; /* 0x0070 */
78 u32 CCGR6; /* 0x0080 */
80 u32 CCGR7; /* 0x0084 */
85 /* Define the bits in register CACRR */
86 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
87 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
88 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7)
89 #define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7)
91 /* Define the bits in register CBCDR */
92 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30)
93 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27
94 #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
95 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27)
96 #define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7)
97 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
98 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
99 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
100 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
101 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22)
102 #define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7)
103 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
104 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
105 #define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19)
106 #define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7)
107 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
108 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
109 #define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16)
110 #define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7)
111 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
112 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
113 #define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13)
114 #define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7)
115 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
116 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
117 #define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10)
118 #define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7)
119 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
120 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
121 #define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8)
122 #define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3)
123 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
124 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
125 #define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6)
126 #define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3)
127 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
128 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
129 #define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3)
130 #define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7)
131 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
132 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
133 #define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7)
134 #define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7)
136 /* Define the bits in register CSCMR1 */
137 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
138 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
139 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30)
140 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3)
141 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
142 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
143 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28)
144 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3)
145 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
146 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
147 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
148 #define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24)
149 #define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3)
150 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
151 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
152 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22)
153 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3)
154 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
155 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
156 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20)
157 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3)
158 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
159 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
160 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
161 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
162 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16)
163 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3)
164 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
165 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
166 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14)
167 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
168 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
169 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
170 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12)
171 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
172 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
173 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
174 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
175 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
176 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8)
177 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
178 #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
179 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
180 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
181 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
182 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4)
183 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
184 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
185 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
186 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2)
187 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3)
188 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
189 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
191 /* Define the bits in register CSCDR2 */
192 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
193 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
194 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25)
195 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7)
196 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
197 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
198 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19)
199 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F)
200 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
201 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
202 #define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16)
203 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
204 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
205 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
206 #define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9)
207 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F)
208 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
209 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6)
210 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6)
211 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7)
212 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0
213 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F
214 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F)
215 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F)
217 /* Define the bits in register CBCMR */
218 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
219 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
220 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14)
221 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
222 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
223 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
224 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12)
225 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
226 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
227 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
228 #define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10)
229 #define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3)
230 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
231 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
232 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8)
233 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
234 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
235 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
236 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6)
237 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3)
238 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
239 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
240 #define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4)
241 #define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
242 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
243 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
245 /* Define the bits in register CSCDR1 */
246 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
247 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
248 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22)
249 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7)
250 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
251 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
252 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19)
253 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7)
254 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
255 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
256 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16)
257 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
258 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
259 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
260 #define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14)
261 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3)
262 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
263 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
264 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11)
265 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7)
266 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
267 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
268 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8)
269 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7)
270 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
271 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
272 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6)
273 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3)
274 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
275 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
276 #define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3)
277 #define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7)
278 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
279 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
280 #define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7)
281 #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7)
283 /* Define the bits in register CCDR */
284 #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
286 /* Define the bits in register CCGRx */
287 #define MXC_CCM_CCGR_CG_MASK 0x3
289 #define MXC_CCM_CCGR4_CG5_OFFSET 10
290 #define MXC_CCM_CCGR4_CG6_OFFSET 12
291 #define MXC_CCM_CCGR5_CG5_OFFSET 10
292 #define MXC_CCM_CCGR2_CG14_OFFSET 28
294 /* Define the bits in register CLPCR */
295 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
297 #define MXC_DPLLC_CTL_HFSM (1 << 7)
298 #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
300 #define MXC_DPLLC_OP_PDF_MASK 0xf
301 #define MXC_DPLLC_OP_MFI_OFFSET 4
302 #define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
303 #define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4)
304 #define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf)
306 #define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff
308 #define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff
310 #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */