2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
24 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
26 #define MXC_CCM_BASE CCM_BASE_ADDR
28 /* DPLL register mapping structure */
44 /* Register maping of CCM*/
50 u32 cacrr; /* 0x0010*/
54 u32 cscmr2; /* 0x0020 */
58 u32 cdcdr; /* 0x0030 */
62 u32 cscdr4; /* 0x0040 */
66 u32 ctor; /* 0x0050 */
70 u32 ccosr; /* 0x0060 */
74 u32 CCGR2; /* 0x0070 */
78 u32 CCGR6; /* 0x0080 */
80 u32 CCGR7; /* 0x0084 */
85 /* Define the bits in register CACRR */
86 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
87 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
89 /* Define the bits in register CBCDR */
90 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30)
91 #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
92 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27
93 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
94 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
95 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
96 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
97 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
98 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
99 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
100 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
101 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
102 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
103 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
104 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
105 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
106 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
107 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
108 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
109 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
110 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
111 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
112 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
114 /* Define the bits in register CSCMR1 */
115 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
116 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
117 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
118 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
119 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26
120 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
121 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
122 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
123 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
124 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
125 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
126 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
127 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
128 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
129 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
130 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
131 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
132 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
133 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
134 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
135 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
136 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
137 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
138 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
139 #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
140 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
141 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
142 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
143 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
144 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
145 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
146 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
148 /* Define the bits in register CSCDR2 */
149 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
150 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
151 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
152 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
153 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
154 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
155 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
156 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
157 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
158 #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
159 #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0
160 #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F
162 /* Define the bits in register CBCMR */
163 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
164 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
165 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
166 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
167 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
168 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
169 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
170 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
171 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
172 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
173 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
174 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
175 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
176 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
178 /* Define the bits in register CSCDR1 */
179 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
180 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
181 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
182 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
183 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
184 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
185 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
186 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
187 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
188 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
189 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
190 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
191 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
192 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
193 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
194 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
195 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
196 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
198 /* Define the bits in register CCDR */
199 #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
201 /* Define the bits in register CCGRx */
202 #define MXC_CCM_CCGR_CG_MASK 0x3
204 #define MXC_CCM_CCGR4_CG5_OFFSET 10
205 #define MXC_CCM_CCGR4_CG6_OFFSET 12
206 #define MXC_CCM_CCGR5_CG5_OFFSET 10
207 #define MXC_CCM_CCGR2_CG14_OFFSET 28
209 /* Define the bits in register CLPCR */
210 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
212 #define MXC_DPLLC_CTL_HFSM (1 << 7)
213 #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
215 #define MXC_DPLLC_OP_PDF_MASK 0xf
216 #define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
217 #define MXC_DPLLC_OP_MFI_OFFSET 4
219 #define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff
221 #define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff
223 #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */