3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #ifndef __MACH_MX35_IOMUX_H__
27 #define __MACH_MX35_IOMUX_H__
29 #include <asm/arch/imx-regs.h>
32 * various IOMUX functions
34 typedef enum iomux_pin_config {
35 MUX_CONFIG_FUNC = 0, /* used as function */
36 MUX_CONFIG_ALT1, /* used as alternate function 1 */
37 MUX_CONFIG_ALT2, /* used as alternate function 2 */
38 MUX_CONFIG_ALT3, /* used as alternate function 3 */
39 MUX_CONFIG_ALT4, /* used as alternate function 4 */
40 MUX_CONFIG_ALT5, /* used as alternate function 5 */
41 MUX_CONFIG_ALT6, /* used as alternate function 6 */
42 MUX_CONFIG_ALT7, /* used as alternate function 7 */
43 MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */
44 MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */
48 * various IOMUX pad functions
50 typedef enum iomux_pad_config {
51 PAD_CTL_DRV_3_3V = 0x0 << 13,
52 PAD_CTL_DRV_1_8V = 0x1 << 13,
53 PAD_CTL_HYS_CMOS = 0x0 << 8,
54 PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
55 PAD_CTL_PKE_NONE = 0x0 << 7,
56 PAD_CTL_PKE_ENABLE = 0x1 << 7,
57 PAD_CTL_PUE_KEEPER = 0x0 << 6,
58 PAD_CTL_PUE_PUD = 0x1 << 6,
59 PAD_CTL_100K_PD = 0x0 << 4,
60 PAD_CTL_47K_PU = 0x1 << 4,
61 PAD_CTL_100K_PU = 0x2 << 4,
62 PAD_CTL_22K_PU = 0x3 << 4,
63 PAD_CTL_ODE_CMOS = 0x0 << 3,
64 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
65 PAD_CTL_DRV_NORMAL = 0x0 << 1,
66 PAD_CTL_DRV_HIGH = 0x1 << 1,
67 PAD_CTL_DRV_MAX = 0x2 << 1,
68 PAD_CTL_SRE_SLOW = 0x0 << 0,
69 PAD_CTL_SRE_FAST = 0x1 << 0
73 * various IOMUX general purpose functions
75 typedef enum iomux_gp_func {
76 MUX_SDCTL_CSD0_SEL = 0x1 << 0,
77 MUX_SDCTL_CSD1_SEL = 0x1 << 1,
78 MUX_TAMPER_DETECT_EN = 0x1 << 2,
82 * various IOMUX input select register index
84 typedef enum iomux_input_select {
85 MUX_IN_AMX_P5_RXCLK = 0,
100 MUX_IN_CSPI2_DATAREADY_B,
107 MUX_IN_EMI_WEIM_DTACK_B,
108 MUX_IN_ESDHC1_DAT4_IN,
109 MUX_IN_ESDHC1_DAT5_IN,
110 MUX_IN_ESDHC1_DAT6_IN,
111 MUX_IN_ESDHC1_DAT7_IN,
112 MUX_IN_ESDHC3_CARD_CLK_IN,
113 MUX_IN_ESDHC3_CMD_IN,
179 MUX_IN_IPU_DISPB_D0_VSYNC,
180 MUX_IN_IPU_DISPB_D12_VSYNC,
181 MUX_IN_IPU_DISPB_SD_D,
182 MUX_IN_IPU_SENSB_DATA_0,
183 MUX_IN_IPU_SENSB_DATA_1,
184 MUX_IN_IPU_SENSB_DATA_2,
185 MUX_IN_IPU_SENSB_DATA_3,
186 MUX_IN_IPU_SENSB_DATA_4,
187 MUX_IN_IPU_SENSB_DATA_5,
188 MUX_IN_IPU_SENSB_DATA_6,
189 MUX_IN_IPU_SENSB_DATA_7,
206 MUX_IN_OWIRE_BATTERY_LINE,
207 MUX_IN_SPDIF_HCKT_CLK2,
208 MUX_IN_SPDIF_SPDIF_IN1,
209 MUX_IN_UART3_UART_RTS_B,
210 MUX_IN_UART3_UART_RXD_MUX,
211 MUX_IN_USB_OTG_DATA_0,
212 MUX_IN_USB_OTG_DATA_1,
213 MUX_IN_USB_OTG_DATA_2,
214 MUX_IN_USB_OTG_DATA_3,
215 MUX_IN_USB_OTG_DATA_4,
216 MUX_IN_USB_OTG_DATA_5,
217 MUX_IN_USB_OTG_DATA_6,
218 MUX_IN_USB_OTG_DATA_7,
221 MUX_IN_USB_UH2_DATA_0,
222 MUX_IN_USB_UH2_DATA_1,
223 MUX_IN_USB_UH2_DATA_2,
224 MUX_IN_USB_UH2_DATA_3,
225 MUX_IN_USB_UH2_DATA_4,
226 MUX_IN_USB_UH2_DATA_5,
227 MUX_IN_USB_UH2_DATA_6,
228 MUX_IN_USB_UH2_DATA_7,
231 MUX_IN_USB_UH2_USB_OC,
232 } iomux_input_select_t;
235 * various IOMUX input functions
237 typedef enum iomux_input_config {
238 INPUT_CTL_PATH0 = 0x0,
249 * Request ownership for an IO pin. This function has to be the first one
250 * being called before that pin is used. The caller has to check the
251 * return value to make sure it returns 0.
253 * @param pin a name defined by iomux_pin_name_t
254 * @param cfg an input function as defined in iomux_pin_cfg_t
256 * @return 0 if successful; Non-zero otherwise
258 void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
261 * Release ownership for an IO pin
263 * @param pin a name defined by iomux_pin_name_t
264 * @param cfg an input function as defined in iomux_pin_cfg_t
266 void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
269 * This function enables/disables the general purpose function for a particular
272 * @param gp one signal as defined in iomux_gp_func_t
273 * @param en 1 to enable; 0 to disable
275 void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
278 * This function configures the pad value for a IOMUX pin.
280 * @param pin a pin number as defined in iomux_pin_name_t
281 * @param config the ORed value of elements defined in
284 void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
287 * This function configures input path.
289 * @param input index of input select register as defined in
290 * iomux_input_select_t
291 * @param config the binary value of elements defined in
294 void mxc_iomux_set_input(iomux_input_select_t input, u32 config);