2 * Freescale i.MX28 GPMI Register Definitions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #ifndef __MX28_REGS_GPMI_H__
27 #define __MX28_REGS_GPMI_H__
29 #include <asm/arch/regs-common.h>
32 struct mx28_gpmi_regs {
33 mx28_reg_32(hw_gpmi_ctrl0)
34 mx28_reg_32(hw_gpmi_compare)
35 mx28_reg_32(hw_gpmi_eccctrl)
36 mx28_reg_32(hw_gpmi_ecccount)
37 mx28_reg_32(hw_gpmi_payload)
38 mx28_reg_32(hw_gpmi_auxiliary)
39 mx28_reg_32(hw_gpmi_ctrl1)
40 mx28_reg_32(hw_gpmi_timing0)
41 mx28_reg_32(hw_gpmi_timing1)
45 mx28_reg_32(hw_gpmi_data)
46 mx28_reg_32(hw_gpmi_stat)
47 mx28_reg_32(hw_gpmi_debug)
48 mx28_reg_32(hw_gpmi_version)
52 #define GPMI_CTRL0_SFTRST (1 << 31)
53 #define GPMI_CTRL0_CLKGATE (1 << 30)
54 #define GPMI_CTRL0_RUN (1 << 29)
55 #define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
56 #define GPMI_CTRL0_LOCK_CS (1 << 27)
57 #define GPMI_CTRL0_UDMA (1 << 26)
58 #define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
59 #define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
60 #define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
61 #define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
62 #define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
63 #define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
64 #define GPMI_CTRL0_WORD_LENGTH (1 << 23)
65 #define GPMI_CTRL0_CS_MASK (0x7 << 20)
66 #define GPMI_CTRL0_CS_OFFSET 20
67 #define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
68 #define GPMI_CTRL0_ADDRESS_OFFSET 17
69 #define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
70 #define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
71 #define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
72 #define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
73 #define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
74 #define GPMI_CTRL0_XFER_COUNT_OFFSET 0
76 #define GPMI_COMPARE_MASK_MASK (0xffff << 16)
77 #define GPMI_COMPARE_MASK_OFFSET 16
78 #define GPMI_COMPARE_REFERENCE_MASK 0xffff
79 #define GPMI_COMPARE_REFERENCE_OFFSET 0
81 #define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
82 #define GPMI_ECCCTRL_HANDLE_OFFSET 16
83 #define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
84 #define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
85 #define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
86 #define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
87 #define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
88 #define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
89 #define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
90 #define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
91 #define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
93 #define GPMI_ECCCOUNT_COUNT_MASK 0xffff
94 #define GPMI_ECCCOUNT_COUNT_OFFSET 0
96 #define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
97 #define GPMI_PAYLOAD_ADDRESS_OFFSET 2
99 #define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
100 #define GPMI_AUXILIARY_ADDRESS_OFFSET 2
102 #define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
103 #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
104 #define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
105 #define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
106 #define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
107 #define GPMI_CTRL1_BCH_MODE (1 << 18)
108 #define GPMI_CTRL1_DLL_ENABLE (1 << 17)
109 #define GPMI_CTRL1_HALF_PERIOD (1 << 16)
110 #define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
111 #define GPMI_CTRL1_RDN_DELAY_OFFSET 12
112 #define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
113 #define GPMI_CTRL1_DEV_IRQ (1 << 10)
114 #define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
115 #define GPMI_CTRL1_BURST_EN (1 << 8)
116 #define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
117 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
118 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
119 #define GPMI_CTRL1_DEV_RESET (1 << 3)
120 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
121 #define GPMI_CTRL1_CAMERA_MODE (1 << 1)
122 #define GPMI_CTRL1_GPMI_MODE (1 << 0)
124 #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
125 #define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
126 #define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
127 #define GPMI_TIMING0_DATA_HOLD_OFFSET 8
128 #define GPMI_TIMING0_DATA_SETUP_MASK 0xff
129 #define GPMI_TIMING0_DATA_SETUP_OFFSET 0
131 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
132 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
134 #define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
135 #define GPMI_TIMING2_UDMA_TRP_OFFSET 24
136 #define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
137 #define GPMI_TIMING2_UDMA_ENV_OFFSET 16
138 #define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
139 #define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
140 #define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
141 #define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
143 #define GPMI_DATA_DATA_MASK 0xffffffff
144 #define GPMI_DATA_DATA_OFFSET 0
146 #define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
147 #define GPMI_STAT_READY_BUSY_OFFSET 24
148 #define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
149 #define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
150 #define GPMI_STAT_DEV7_ERROR (1 << 15)
151 #define GPMI_STAT_DEV6_ERROR (1 << 14)
152 #define GPMI_STAT_DEV5_ERROR (1 << 13)
153 #define GPMI_STAT_DEV4_ERROR (1 << 12)
154 #define GPMI_STAT_DEV3_ERROR (1 << 11)
155 #define GPMI_STAT_DEV2_ERROR (1 << 10)
156 #define GPMI_STAT_DEV1_ERROR (1 << 9)
157 #define GPMI_STAT_DEV0_ERROR (1 << 8)
158 #define GPMI_STAT_ATA_IRQ (1 << 4)
159 #define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
160 #define GPMI_STAT_FIFO_EMPTY (1 << 2)
161 #define GPMI_STAT_FIFO_FULL (1 << 1)
162 #define GPMI_STAT_PRESENT (1 << 0)
164 #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
165 #define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
166 #define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
167 #define GPMI_DEBUG_DMA_SENSE_OFFSET 16
168 #define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
169 #define GPMI_DEBUG_DMAREQ_OFFSET 8
170 #define GPMI_DEBUG_CMD_END_MASK 0xff
171 #define GPMI_DEBUG_CMD_END_OFFSET 0
173 #define GPMI_VERSION_MAJOR_MASK (0xff << 24)
174 #define GPMI_VERSION_MAJOR_OFFSET 24
175 #define GPMI_VERSION_MINOR_MASK (0xff << 16)
176 #define GPMI_VERSION_MINOR_OFFSET 16
177 #define GPMI_VERSION_STEP_MASK 0xffff
178 #define GPMI_VERSION_STEP_OFFSET 0
180 #define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
181 #define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
182 #define GPMI_DEBUG2_BUSY (1 << 23)
183 #define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
184 #define GPMI_DEBUG2_PIN_STATE_OFFSET 20
185 #define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
186 #define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
187 #define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
188 #define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
189 #define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
190 #define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
191 #define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
192 #define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
193 #define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
194 #define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
195 #define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
196 #define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
197 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
198 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
199 #define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
200 #define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
201 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
202 #define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
203 #define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
204 #define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
205 #define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
206 #define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
207 #define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
208 #define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
209 #define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
210 #define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
211 #define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
212 #define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
213 #define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
214 #define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
215 #define GPMI_DEBUG2_RDN_TAP_OFFSET 0
217 #define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
218 #define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
219 #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
220 #define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
222 #endif /* __MX28_REGS_GPMI_H__ */