2 * iopin settings are controlled by four different sets of registers
4 * individual iopad setup (voltage select, pull/keep, drive strength ...)
5 * group iopad setup (same as above but for groups of signals)
6 * input select when multiple inputs are possible
10 * software pad mux control
12 /* SW Input On (Loopback) */
13 #define MX25_PIN_MUX_SION (1 << 4)
15 #define MX25_PIN_MUX_MODE(mode) ((mode & 0x7) << 0)
16 struct iomuxc_mux_ctl {
159 * software pad control
161 /* Select 3.3 or 1.8 volts */
162 #define MX25_PIN_PAD_CTL_DVS_33 (0 << 13)
163 #define MX25_PIN_PAD_CTL_DVS_18 (1 << 13)
164 /* Enable hysteresis */
165 #define MX25_PIN_PAD_CTL_HYS (1 << 8)
166 /* Enable pull/keeper */
167 #define MX25_PIN_PAD_CTL_PKE (1 << 7)
168 /* 0 - keeper / 1 - pull */
169 #define MX25_PIN_PAD_CTL_PUE (1 << 6)
170 /* pull up/down strength */
171 #define MX25_PIN_PAD_CTL_100K_PD (0 << 4)
172 #define MX25_PIN_PAD_CTL_47K_PU (1 << 4)
173 #define MX25_PIN_PAD_CTL_100K_PU (2 << 4)
174 #define MX25_PIN_PAD_CTL_22K_PU (3 << 4)
175 /* open drain control */
176 #define MX25_PIN_PAD_CTL_OD (1 << 3)
178 #define MX25_PIN_PAD_CTL_DS_NOM (0 << 1)
179 #define MX25_PIN_PAD_CTL_DS_HIGH (1 << 1)
180 #define MX25_PIN_PAD_CTL_DS_MAX (2 << 1)
181 #define MX25_PIN_PAD_CTL_DS_MAX11 (3 << 1)
183 #define MX25_PIN_PAD_CTL_SRE_SLOW (0 << 0)
184 #define MX25_PIN_PAD_CTL_SRE_FAST (1 << 0)
185 struct iomuxc_pad_ctl {
313 * Pad group drive strength and voltage select
314 * Same fields as iomuxc_pad_ctl plus ddr type
316 /* Select DDR type */
317 #define MX25_PIN_PAD_CTL_DDR_18 (0 << 11)
318 #define MX25_PIN_PAD_CTL_DDR_33 (1 << 11)
319 #define MX25_PIN_PAD_CTL_DDR_MAX (2 << 11)
320 struct iomuxc_pad_grp_ctl {
342 * Pad input select control
343 * Select which pad to connect to an input port
344 * where multiple pads can function as given input
346 #define MX25_PAD_INPUT_SELECT_DAISY(in) ((in & 0x7) << 0)
347 struct iomuxc_pad_input_select {
348 u32 audmux_p4_input_da_amx;
349 u32 audmux_p4_input_db_amx;
350 u32 audmux_p4_input_rxclk_amx;
351 u32 audmux_p4_input_rxfs_amx;
352 u32 audmux_p4_input_txclk_amx;
353 u32 audmux_p4_input_txfs_amx;
354 u32 audmux_p7_input_da_amx;
355 u32 audmux_p7_input_txfs_amx;
356 u32 can1_ipp_ind_canrx;
357 u32 can2_ipp_ind_canrx;
360 u32 cspi1_ipp_ind_ss3_b;
361 u32 cspi2_ipp_cspi_clk_in;
362 u32 cspi2_ipp_ind_dataready_b;
363 u32 cspi2_ipp_ind_miso;
364 u32 cspi2_ipp_ind_mosi;
365 u32 cspi2_ipp_ind_ss0_b;
366 u32 cspi2_ipp_ind_ss1_b;
367 u32 cspi3_ipp_cspi_clk_in;
368 u32 cspi3_ipp_ind_dataready_b;
369 u32 cspi3_ipp_ind_miso;
370 u32 cspi3_ipp_ind_mosi;
371 u32 cspi3_ipp_ind_ss0_b;
372 u32 cspi3_ipp_ind_ss1_b;
373 u32 cspi3_ipp_ind_ss2_b;
374 u32 cspi3_ipp_ind_ss3_b;
375 u32 esdhc1_ipp_dat4_in;
376 u32 esdhc1_ipp_dat5_in;
377 u32 esdhc1_ipp_dat6_in;
378 u32 esdhc1_ipp_dat7_in;
379 u32 esdhc2_ipp_card_clk_in;
380 u32 esdhc2_ipp_cmd_in;
381 u32 esdhc2_ipp_dat0_in;
382 u32 esdhc2_ipp_dat1_in;
383 u32 esdhc2_ipp_dat2_in;
384 u32 esdhc2_ipp_dat3_in;
385 u32 esdhc2_ipp_dat4_in;
386 u32 esdhc2_ipp_dat5_in;
387 u32 esdhc2_ipp_dat6_in;
388 u32 esdhc2_ipp_dat7_in;
399 u32 kpp_ipp_ind_col_4;
400 u32 kpp_ipp_ind_col_5;
401 u32 kpp_ipp_ind_col_6;
402 u32 kpp_ipp_ind_col_7;
403 u32 kpp_ipp_ind_row_4;
404 u32 kpp_ipp_ind_row_5;
405 u32 kpp_ipp_ind_row_6;
406 u32 kpp_ipp_ind_row_7;
407 u32 sim1_pin_sim_rcvd1_in;
408 u32 sim1_pin_sim_simpd1;
409 u32 sim1_sim_rcvd1_io;
410 u32 sim2_pin_sim_rcvd1_in;
411 u32 sim2_pin_sim_simpd1;
412 u32 sim2_sim_rcvd1_io;
413 u32 uart3_ipp_uart_rts_b;
414 u32 uart3_ipp_uart_rxd_mux;
415 u32 uart4_ipp_uart_rts_b;
416 u32 uart4_ipp_uart_rxd_mux;
417 u32 uart5_ipp_uart_rts_b;
418 u32 uart5_ipp_uart_rxd_mux;
419 u32 usb_top_ipp_ind_otg_usb_oc;
420 u32 usb_top_ipp_ind_uh2_usb_oc;