2 * Copyright (C) 2009, DENX Software Engineering
3 * Author: John Rigby <jcrigby@gmail.com
5 * Based on arch-mx31/mx31-regs.h
6 * Copyright (C) 2009 Ilya Yanok,
7 * Emcraft Systems <yanok@emcraft.com>
8 * and arch-mx27/imx-regs.h
9 * Copyright (C) 2007 Pengutronix,
10 * Sascha Hauer <s.hauer@pengutronix.de>
11 * Copyright (C) 2009 Ilya Yanok,
12 * Emcraft Systems <yanok@emcraft.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 extern void mx25_fec_init_pins(void);
39 extern void imx_get_mac_from_fuse(unsigned char *mac);
42 /* Clock Control Module (CCM) registers */
44 u32 mpctl; /* Core PLL Control */
45 u32 upctl; /* USB PLL Control */
46 u32 cctl; /* Clock Control */
47 u32 cgr0; /* Clock Gating Control 0 */
48 u32 cgr1; /* Clock Gating Control 1 */
49 u32 cgr2; /* Clock Gating Control 2 */
50 u32 pcdr[4]; /* PER Clock Dividers */
51 u32 rcsr; /* CCM Status */
52 u32 crdr; /* CCM Reset and Debug */
53 u32 dcvr0; /* DPTC Comparator Value 0 */
54 u32 dcvr1; /* DPTC Comparator Value 1 */
55 u32 dcvr2; /* DPTC Comparator Value 2 */
56 u32 dcvr3; /* DPTC Comparator Value 3 */
57 u32 ltr0; /* Load Tracking 0 */
58 u32 ltr1; /* Load Tracking 1 */
59 u32 ltr2; /* Load Tracking 2 */
60 u32 ltr3; /* Load Tracking 3 */
61 u32 ltbr0; /* Load Tracking Buffer 0 */
62 u32 ltbr1; /* Load Tracking Buffer 1 */
63 u32 pcmr0; /* Power Management Control 0 */
64 u32 pcmr1; /* Power Management Control 1 */
65 u32 pcmr2; /* Power Management Control 2 */
66 u32 mcr; /* Miscellaneous Control */
67 u32 lpimr0; /* Low Power Interrupt Mask 0 */
68 u32 lpimr1; /* Low Power Interrupt Mask 1 */
71 /* Enhanced SDRAM Controller (ESDRAMC) registers */
73 u32 ctl0; /* control 0 */
74 u32 cfg0; /* configuration 0 */
75 u32 ctl1; /* control 1 */
76 u32 cfg1; /* configuration 1 */
77 u32 misc; /* miscellaneous */
79 u32 cdly1; /* Delay Line 1 configuration debug */
80 u32 cdly2; /* delay line 2 configuration debug */
81 u32 cdly3; /* delay line 3 configuration debug */
82 u32 cdly4; /* delay line 4 configuration debug */
83 u32 cdly5; /* delay line 5 configuration debug */
84 u32 cdlyl; /* delay line cycle length debug */
90 u32 dir; /* direction */
91 u32 psr; /* pad satus */
92 u32 icr1; /* interrupt config 1 */
93 u32 icr2; /* interrupt config 2 */
94 u32 imr; /* interrupt mask */
95 u32 isr; /* interrupt status */
96 u32 edge_sel; /* edge select */
99 /* General Purpose Timer (GPT) registers */
101 u32 ctrl; /* control */
102 u32 pre; /* prescaler */
103 u32 stat; /* status */
104 u32 intr; /* interrupt */
105 u32 cmp[3]; /* output compare 1-3 */
106 u32 capt[2]; /* input capture 1-2 */
107 u32 counter; /* counter */
110 /* Watchdog Timer (WDOG) registers */
112 u16 wcr; /* Control */
113 u16 wsr; /* Service */
114 u16 wrsr; /* Reset Status */
115 u16 wicr; /* Interrupt Control */
116 u16 wmcr; /* Misc Control */
119 /* IIM control registers */
139 struct fuse_bank0_regs {
147 #define IMX_AIPS1_BASE (0x43F00000)
148 #define IMX_MAX_BASE (0x43F04000)
149 #define IMX_CLKCTL_BASE (0x43F08000)
150 #define IMX_ETB_SLOT4_BASE (0x43F0C000)
151 #define IMX_ETB_SLOT5_BASE (0x43F10000)
152 #define IMX_ECT_CTIO_BASE (0x43F18000)
153 #define IMX_I2C_BASE (0x43F80000)
154 #define IMX_I2C3_BASE (0x43F84000)
155 #define IMX_CAN1_BASE (0x43F88000)
156 #define IMX_CAN2_BASE (0x43F8C000)
157 #define IMX_UART1_BASE (0x43F90000)
158 #define IMX_UART2_BASE (0x43F94000)
159 #define IMX_I2C2_BASE (0x43F98000)
160 #define IMX_OWIRE_BASE (0x43F9C000)
161 #define IMX_CSPI1_BASE (0x43FA4000)
162 #define IMX_KPP_BASE (0x43FA8000)
163 #define IMX_IOPADMUX_BASE (0x43FAC000)
164 #define IMX_IOPADCTL_BASE (0x43FAC22C)
165 #define IMX_IOPADGRPCTL_BASE (0x43FAC418)
166 #define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
167 #define IMX_AUDMUX_BASE (0x43FB0000)
168 #define IMX_ECT_IP1_BASE (0x43FB8000)
169 #define IMX_ECT_IP2_BASE (0x43FBC000)
172 #define IMX_SPBA_BASE (0x50000000)
173 #define IMX_CSPI3_BASE (0x50004000)
174 #define IMX_UART4_BASE (0x50008000)
175 #define IMX_UART3_BASE (0x5000C000)
176 #define IMX_CSPI2_BASE (0x50010000)
177 #define IMX_SSI2_BASE (0x50014000)
178 #define IMX_ESAI_BASE (0x50018000)
179 #define IMX_ATA_DMA_BASE (0x50020000)
180 #define IMX_SIM1_BASE (0x50024000)
181 #define IMX_SIM2_BASE (0x50028000)
182 #define IMX_UART5_BASE (0x5002C000)
183 #define IMX_TSC_BASE (0x50030000)
184 #define IMX_SSI1_BASE (0x50034000)
185 #define IMX_FEC_BASE (0x50038000)
186 #define IMX_SPBA_CTRL_BASE (0x5003C000)
189 #define IMX_AIPS2_BASE (0x53F00000)
190 #define IMX_CCM_BASE (0x53F80000)
191 #define IMX_GPT4_BASE (0x53F84000)
192 #define IMX_GPT3_BASE (0x53F88000)
193 #define IMX_GPT2_BASE (0x53F8C000)
194 #define IMX_GPT1_BASE (0x53F90000)
195 #define IMX_EPIT1_BASE (0x53F94000)
196 #define IMX_EPIT2_BASE (0x53F98000)
197 #define IMX_GPIO4_BASE (0x53F9C000)
198 #define IMX_PWM2_BASE (0x53FA0000)
199 #define IMX_GPIO3_BASE (0x53FA4000)
200 #define IMX_PWM3_BASE (0x53FA8000)
201 #define IMX_SCC_BASE (0x53FAC000)
202 #define IMX_SCM_BASE (0x53FAE000)
203 #define IMX_SMN_BASE (0x53FAF000)
204 #define IMX_RNGD_BASE (0x53FB0000)
205 #define IMX_MMC_SDHC1_BASE (0x53FB4000)
206 #define IMX_MMC_SDHC2_BASE (0x53FB8000)
207 #define IMX_LCDC_BASE (0x53FBC000)
208 #define IMX_SLCDC_BASE (0x53FC0000)
209 #define IMX_PWM4_BASE (0x53FC8000)
210 #define IMX_GPIO1_BASE (0x53FCC000)
211 #define IMX_GPIO2_BASE (0x53FD0000)
212 #define IMX_SDMA_BASE (0x53FD4000)
213 #define IMX_WDT_BASE (0x53FDC000)
214 #define IMX_PWM1_BASE (0x53FE0000)
215 #define IMX_RTIC_BASE (0x53FEC000)
216 #define IMX_IIM_BASE (0x53FF0000)
217 #define IMX_USB_BASE (0x53FF4000)
218 #define IMX_CSI_BASE (0x53FF8000)
219 #define IMX_DRYICE_BASE (0x53FFC000)
221 #define IMX_ARM926_ROMPATCH (0x60000000)
222 #define IMX_ARM926_ASIC (0x68000000)
224 /* 128K Internal Static RAM */
225 #define IMX_RAM_BASE (0x78000000)
228 #define IMX_SDRAM_BANK0_BASE (0x80000000)
229 #define IMX_SDRAM_BANK1_BASE (0x90000000)
231 #define IMX_WEIM_CS0 (0xA0000000)
232 #define IMX_WEIM_CS1 (0xA8000000)
233 #define IMX_WEIM_CS2 (0xB0000000)
234 #define IMX_WEIM_CS3 (0xB2000000)
235 #define IMX_WEIM_CS4 (0xB4000000)
236 #define IMX_ESDRAMC_BASE (0xB8001000)
237 #define IMX_WEIM_CTRL_BASE (0xB8002000)
238 #define IMX_M3IF_CTRL_BASE (0xB8003000)
239 #define IMX_EMI_CTRL_BASE (0xB8004000)
241 /* NAND Flash Controller */
242 #define IMX_NFC_BASE (0xBB000000)
243 #define NFC_BASE_ADDR IMX_NFC_BASE
246 #define CCM_PLL_MFI_SHIFT 10
247 #define CCM_PLL_MFI_MASK 0xf
248 #define CCM_PLL_MFN_SHIFT 0
249 #define CCM_PLL_MFN_MASK 0x3ff
250 #define CCM_PLL_MFD_SHIFT 16
251 #define CCM_PLL_MFD_MASK 0x3ff
252 #define CCM_PLL_PD_SHIFT 26
253 #define CCM_PLL_PD_MASK 0xf
254 #define CCM_CCTL_ARM_DIV_SHIFT 30
255 #define CCM_CCTL_ARM_DIV_MASK 3
256 #define CCM_CCTL_AHB_DIV_SHIFT 28
257 #define CCM_CCTL_AHB_DIV_MASK 3
258 #define CCM_CCTL_ARM_SRC (1 << 14)
259 #define CCM_CGR1_GPT1 (1 << 19)
260 #define CCM_PERCLK_REG(clk) (clk / 4)
261 #define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4))
262 #define CCM_PERCLK_MASK 0x3f
263 #define CCM_RCSR_NF_16BIT_SEL (1 << 14)
264 #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
266 /* ESDRAM Controller register bitfields */
267 #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
268 #define ESDCTL_BL (1 << 7)
269 #define ESDCTL_FP (1 << 8)
270 #define ESDCTL_PWDT(x) (((x) & 3) << 10)
271 #define ESDCTL_SREFR(x) (((x) & 7) << 13)
272 #define ESDCTL_DSIZ_16_UPPER (0 << 16)
273 #define ESDCTL_DSIZ_16_LOWER (1 << 16)
274 #define ESDCTL_DSIZ_32 (2 << 16)
275 #define ESDCTL_COL8 (0 << 20)
276 #define ESDCTL_COL9 (1 << 20)
277 #define ESDCTL_COL10 (2 << 20)
278 #define ESDCTL_ROW11 (0 << 24)
279 #define ESDCTL_ROW12 (1 << 24)
280 #define ESDCTL_ROW13 (2 << 24)
281 #define ESDCTL_ROW14 (3 << 24)
282 #define ESDCTL_ROW15 (4 << 24)
283 #define ESDCTL_SP (1 << 27)
284 #define ESDCTL_SMODE_NORMAL (0 << 28)
285 #define ESDCTL_SMODE_PRECHARGE (1 << 28)
286 #define ESDCTL_SMODE_AUTO_REF (2 << 28)
287 #define ESDCTL_SMODE_LOAD_MODE (3 << 28)
288 #define ESDCTL_SMODE_MAN_REF (4 << 28)
289 #define ESDCTL_SDE (1 << 31)
291 #define ESDCFG_TRC(x) (((x) & 0xf) << 0)
292 #define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
293 #define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
294 #define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
295 #define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
296 #define ESDCFG_TWR (1 << 15)
297 #define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
298 #define ESDCFG_TRP(x) (((x) & 0x3) << 18)
299 #define ESDCFG_TWTR (1 << 20)
300 #define ESDCFG_TXP(x) (((x) & 0x3) << 21)
302 #define ESDMISC_RST (1 << 1)
303 #define ESDMISC_MDDREN (1 << 2)
304 #define ESDMISC_MDDR_DL_RST (1 << 3)
305 #define ESDMISC_MDDR_MDIS (1 << 4)
306 #define ESDMISC_LHD (1 << 5)
307 #define ESDMISC_MA10_SHARE (1 << 6)
308 #define ESDMISC_SDRAM_RDY (1 << 31)
311 #define GPT_CTRL_SWR (1 << 15) /* Software reset */
312 #define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */
313 #define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */
314 #define GPT_CTRL_TEN 1 /* Timer enable */
318 #define WSR_UNLOCK1 0x5555
319 #define WSR_UNLOCK2 0xAAAA
321 #endif /* _IMX_REGS_H */