2 * Copyright (C) 2009, DENX Software Engineering
3 * Author: John Rigby <jcrigby@gmail.com
5 * Based on arch-mx31/imx-regs.h
6 * Copyright (C) 2009 Ilya Yanok,
7 * Emcraft Systems <yanok@emcraft.com>
8 * and arch-mx27/imx-regs.h
9 * Copyright (C) 2007 Pengutronix,
10 * Sascha Hauer <s.hauer@pengutronix.de>
11 * Copyright (C) 2009 Ilya Yanok,
12 * Emcraft Systems <yanok@emcraft.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
37 #include <asm/types.h>
39 /* Clock Control Module (CCM) registers */
41 u32 mpctl; /* Core PLL Control */
42 u32 upctl; /* USB PLL Control */
43 u32 cctl; /* Clock Control */
44 u32 cgr0; /* Clock Gating Control 0 */
45 u32 cgr1; /* Clock Gating Control 1 */
46 u32 cgr2; /* Clock Gating Control 2 */
47 u32 pcdr[4]; /* PER Clock Dividers */
48 u32 rcsr; /* CCM Status */
49 u32 crdr; /* CCM Reset and Debug */
50 u32 dcvr0; /* DPTC Comparator Value 0 */
51 u32 dcvr1; /* DPTC Comparator Value 1 */
52 u32 dcvr2; /* DPTC Comparator Value 2 */
53 u32 dcvr3; /* DPTC Comparator Value 3 */
54 u32 ltr0; /* Load Tracking 0 */
55 u32 ltr1; /* Load Tracking 1 */
56 u32 ltr2; /* Load Tracking 2 */
57 u32 ltr3; /* Load Tracking 3 */
58 u32 ltbr0; /* Load Tracking Buffer 0 */
59 u32 ltbr1; /* Load Tracking Buffer 1 */
60 u32 pcmr0; /* Power Management Control 0 */
61 u32 pcmr1; /* Power Management Control 1 */
62 u32 pcmr2; /* Power Management Control 2 */
63 u32 mcr; /* Miscellaneous Control */
64 u32 lpimr0; /* Low Power Interrupt Mask 0 */
65 u32 lpimr1; /* Low Power Interrupt Mask 1 */
68 /* Enhanced SDRAM Controller (ESDRAMC) registers */
70 u32 ctl0; /* control 0 */
71 u32 cfg0; /* configuration 0 */
72 u32 ctl1; /* control 1 */
73 u32 cfg1; /* configuration 1 */
74 u32 misc; /* miscellaneous */
76 u32 cdly1; /* Delay Line 1 configuration debug */
77 u32 cdly2; /* delay line 2 configuration debug */
78 u32 cdly3; /* delay line 3 configuration debug */
79 u32 cdly4; /* delay line 4 configuration debug */
80 u32 cdly5; /* delay line 5 configuration debug */
81 u32 cdlyl; /* delay line cycle length debug */
84 /* General Purpose Timer (GPT) registers */
86 u32 ctrl; /* control */
87 u32 pre; /* prescaler */
88 u32 stat; /* status */
89 u32 intr; /* interrupt */
90 u32 cmp[3]; /* output compare 1-3 */
91 u32 capt[2]; /* input capture 1-2 */
92 u32 counter; /* counter */
95 /* Watchdog Timer (WDOG) registers */
97 u16 wcr; /* Control */
98 u16 wsr; /* Service */
99 u16 wrsr; /* Reset Status */
100 u16 wicr; /* Interrupt Control */
101 u16 wmcr; /* Misc Control */
104 /* IIM control registers */
128 struct fuse_bank0_regs {
135 struct fuse_bank1_regs {
142 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
175 /* AHB <-> IP-Bus Interface (AIPS) */
186 #define IMX_AIPS1_BASE (0x43F00000)
187 #define IMX_MAX_BASE (0x43F04000)
188 #define IMX_CLKCTL_BASE (0x43F08000)
189 #define IMX_ETB_SLOT4_BASE (0x43F0C000)
190 #define IMX_ETB_SLOT5_BASE (0x43F10000)
191 #define IMX_ECT_CTIO_BASE (0x43F18000)
192 #define IMX_I2C_BASE (0x43F80000)
193 #define IMX_I2C3_BASE (0x43F84000)
194 #define IMX_CAN1_BASE (0x43F88000)
195 #define IMX_CAN2_BASE (0x43F8C000)
196 #define UART1_BASE (0x43F90000)
197 #define UART2_BASE (0x43F94000)
198 #define IMX_I2C2_BASE (0x43F98000)
199 #define IMX_OWIRE_BASE (0x43F9C000)
200 #define IMX_CSPI1_BASE (0x43FA4000)
201 #define IMX_KPP_BASE (0x43FA8000)
202 #define IMX_IOPADMUX_BASE (0x43FAC000)
203 #define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE
204 #define IMX_IOPADCTL_BASE (0x43FAC22C)
205 #define IMX_IOPADGRPCTL_BASE (0x43FAC418)
206 #define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
207 #define IMX_AUDMUX_BASE (0x43FB0000)
208 #define IMX_ECT_IP1_BASE (0x43FB8000)
209 #define IMX_ECT_IP2_BASE (0x43FBC000)
212 #define IMX_SPBA_BASE (0x50000000)
213 #define IMX_CSPI3_BASE (0x50004000)
214 #define UART4_BASE (0x50008000)
215 #define UART3_BASE (0x5000C000)
216 #define IMX_CSPI2_BASE (0x50010000)
217 #define IMX_SSI2_BASE (0x50014000)
218 #define IMX_ESAI_BASE (0x50018000)
219 #define IMX_ATA_DMA_BASE (0x50020000)
220 #define IMX_SIM1_BASE (0x50024000)
221 #define IMX_SIM2_BASE (0x50028000)
222 #define UART5_BASE (0x5002C000)
223 #define IMX_TSC_BASE (0x50030000)
224 #define IMX_SSI1_BASE (0x50034000)
225 #define IMX_FEC_BASE (0x50038000)
226 #define IMX_SPBA_CTRL_BASE (0x5003C000)
229 #define IMX_AIPS2_BASE (0x53F00000)
230 #define IMX_CCM_BASE (0x53F80000)
231 #define IMX_GPT4_BASE (0x53F84000)
232 #define IMX_GPT3_BASE (0x53F88000)
233 #define IMX_GPT2_BASE (0x53F8C000)
234 #define IMX_GPT1_BASE (0x53F90000)
235 #define IMX_EPIT1_BASE (0x53F94000)
236 #define IMX_EPIT2_BASE (0x53F98000)
237 #define IMX_GPIO4_BASE (0x53F9C000)
238 #define IMX_PWM2_BASE (0x53FA0000)
239 #define IMX_GPIO3_BASE (0x53FA4000)
240 #define IMX_PWM3_BASE (0x53FA8000)
241 #define IMX_SCC_BASE (0x53FAC000)
242 #define IMX_SCM_BASE (0x53FAE000)
243 #define IMX_SMN_BASE (0x53FAF000)
244 #define IMX_RNGD_BASE (0x53FB0000)
245 #define IMX_MMC_SDHC1_BASE (0x53FB4000)
246 #define IMX_MMC_SDHC2_BASE (0x53FB8000)
247 #define IMX_LCDC_BASE (0x53FBC000)
248 #define IMX_SLCDC_BASE (0x53FC0000)
249 #define IMX_PWM4_BASE (0x53FC8000)
250 #define IMX_GPIO1_BASE (0x53FCC000)
251 #define IMX_GPIO2_BASE (0x53FD0000)
252 #define IMX_SDMA_BASE (0x53FD4000)
253 #define IMX_WDT_BASE (0x53FDC000)
254 #define IMX_PWM1_BASE (0x53FE0000)
255 #define IMX_RTIC_BASE (0x53FEC000)
256 #define IMX_IIM_BASE (0x53FF0000)
257 #define IIM_BASE_ADDR IMX_IIM_BASE
258 #define IMX_USB_BASE (0x53FF4000)
259 #define IMX_USB_PORT_OFFSET 0x200
260 #define IMX_CSI_BASE (0x53FF8000)
261 #define IMX_DRYICE_BASE (0x53FFC000)
263 #define IMX_ARM926_ROMPATCH (0x60000000)
264 #define IMX_ARM926_ASIC (0x68000000)
266 /* 128K Internal Static RAM */
267 #define IMX_RAM_BASE (0x78000000)
268 #define IMX_RAM_SIZE (128 * 1024)
271 #define IMX_SDRAM_BANK0_BASE (0x80000000)
272 #define IMX_SDRAM_BANK1_BASE (0x90000000)
274 #define IMX_WEIM_CS0 (0xA0000000)
275 #define IMX_WEIM_CS1 (0xA8000000)
276 #define IMX_WEIM_CS2 (0xB0000000)
277 #define IMX_WEIM_CS3 (0xB2000000)
278 #define IMX_WEIM_CS4 (0xB4000000)
279 #define IMX_ESDRAMC_BASE (0xB8001000)
280 #define IMX_WEIM_CTRL_BASE (0xB8002000)
281 #define IMX_M3IF_CTRL_BASE (0xB8003000)
282 #define IMX_EMI_CTRL_BASE (0xB8004000)
284 /* NAND Flash Controller */
285 #define IMX_NFC_BASE (0xBB000000)
286 #define NFC_BASE_ADDR IMX_NFC_BASE
289 #define CCM_PLL_MFI_SHIFT 10
290 #define CCM_PLL_MFI_MASK 0xf
291 #define CCM_PLL_MFN_SHIFT 0
292 #define CCM_PLL_MFN_MASK 0x3ff
293 #define CCM_PLL_MFD_SHIFT 16
294 #define CCM_PLL_MFD_MASK 0x3ff
295 #define CCM_PLL_PD_SHIFT 26
296 #define CCM_PLL_PD_MASK 0xf
297 #define CCM_CCTL_ARM_DIV_SHIFT 30
298 #define CCM_CCTL_ARM_DIV_MASK 3
299 #define CCM_CCTL_AHB_DIV_SHIFT 28
300 #define CCM_CCTL_AHB_DIV_MASK 3
301 #define CCM_CCTL_ARM_SRC (1 << 14)
302 #define CCM_CGR1_GPT1 (1 << 19)
303 #define CCM_PERCLK_REG(clk) (clk / 4)
304 #define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4))
305 #define CCM_PERCLK_MASK 0x3f
306 #define CCM_RCSR_NF_16BIT_SEL (1 << 14)
307 #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
309 /* ESDRAM Controller register bitfields */
310 #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
311 #define ESDCTL_BL (1 << 7)
312 #define ESDCTL_FP (1 << 8)
313 #define ESDCTL_PWDT(x) (((x) & 3) << 10)
314 #define ESDCTL_SREFR(x) (((x) & 7) << 13)
315 #define ESDCTL_DSIZ_16_UPPER (0 << 16)
316 #define ESDCTL_DSIZ_16_LOWER (1 << 16)
317 #define ESDCTL_DSIZ_32 (2 << 16)
318 #define ESDCTL_COL8 (0 << 20)
319 #define ESDCTL_COL9 (1 << 20)
320 #define ESDCTL_COL10 (2 << 20)
321 #define ESDCTL_ROW11 (0 << 24)
322 #define ESDCTL_ROW12 (1 << 24)
323 #define ESDCTL_ROW13 (2 << 24)
324 #define ESDCTL_ROW14 (3 << 24)
325 #define ESDCTL_ROW15 (4 << 24)
326 #define ESDCTL_SP (1 << 27)
327 #define ESDCTL_SMODE_NORMAL (0 << 28)
328 #define ESDCTL_SMODE_PRECHARGE (1 << 28)
329 #define ESDCTL_SMODE_AUTO_REF (2 << 28)
330 #define ESDCTL_SMODE_LOAD_MODE (3 << 28)
331 #define ESDCTL_SMODE_MAN_REF (4 << 28)
332 #define ESDCTL_SDE (1 << 31)
334 #define ESDCFG_TRC(x) (((x) & 0xf) << 0)
335 #define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
336 #define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
337 #define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
338 #define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
339 #define ESDCFG_TWR (1 << 15)
340 #define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
341 #define ESDCFG_TRP(x) (((x) & 0x3) << 18)
342 #define ESDCFG_TWTR (1 << 20)
343 #define ESDCFG_TXP(x) (((x) & 0x3) << 21)
345 #define ESDMISC_RST (1 << 1)
346 #define ESDMISC_MDDREN (1 << 2)
347 #define ESDMISC_MDDR_DL_RST (1 << 3)
348 #define ESDMISC_MDDR_MDIS (1 << 4)
349 #define ESDMISC_LHD (1 << 5)
350 #define ESDMISC_MA10_SHARE (1 << 6)
351 #define ESDMISC_SDRAM_RDY (1 << 31)
354 #define GPT_CTRL_SWR (1 << 15) /* Software reset */
355 #define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */
356 #define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */
357 #define GPT_CTRL_TEN 1 /* Timer enable */
361 #define WSR_UNLOCK1 0x5555
362 #define WSR_UNLOCK2 0xAAAA
364 /* Names used in GPIO driver */
365 #define GPIO1_BASE_ADDR IMX_GPIO1_BASE
366 #define GPIO2_BASE_ADDR IMX_GPIO2_BASE
367 #define GPIO3_BASE_ADDR IMX_GPIO3_BASE
368 #define GPIO4_BASE_ADDR IMX_GPIO4_BASE
370 #define CHIP_REV_1_0 0x10
371 #define CHIP_REV_1_1 0x11
372 #define CHIP_REV_1_2 0x12
374 #endif /* _IMX_REGS_H */