6 * Author : Carsten Schneider, mycable GmbH
10 * Matthias Weisser <weisserm@arcor.de>
12 * SPDX-License-Identifier: GPL-2.0+
43 /* The mb86r0x chip control (CCNT) register set. */
69 /* The mb86r0x clock reset generator */
84 /* The mb86r0x timer */
85 struct mb86r0x_timer {
95 /* mb86r0x gdc display controller */
96 struct mb86r0x_gdc_dsp {
97 /* Display settings */
183 /* Display settings */
189 /* Layer 0 extended */
197 /* Layer 1 extended */
205 /* Layer 2 extended */
213 /* Layer 3 extended */
221 /* Layer 4 extended */
229 /* Layer 5 extended */
237 /* Multi screen control */
251 /* Extended transparency control */
260 /* YUV coefficients */
285 /* mb86r0x gdc capture controller */
286 struct mb86r0x_gdc_cap {
322 uint32_t pad08[12 + 1984];
325 /* mb86r0x gdc draw */
326 struct mb86r0x_gdc_draw {
443 /* mb86r0x gdc geometry engine */
444 struct mb86r0x_gdc_geom {
469 uint32_t pad04[16*1024 - 19];
470 struct mb86r0x_gdc_dsp dsp0;
471 struct mb86r0x_gdc_dsp dsp1;
472 uint32_t pad05[4*1024 - 2];
475 struct mb86r0x_gdc_cap cap0;
476 struct mb86r0x_gdc_cap cap1;
477 uint32_t pad06[4*1024];
478 uint32_t texture_base[16*1024];
479 struct mb86r0x_gdc_draw draw;
480 uint32_t pad07[7*1024];
481 struct mb86r0x_gdc_geom geom;
482 uint32_t pad08[7*1024];
486 struct mb86r0x_ddr2c {
521 struct mb86r0x_memc {
527 #endif /* __ASSEMBLY__ */
530 * Physical Address Defines
532 #define MB86R0x_DDR2_BASE 0xf3000000
533 #define MB86R0x_GDC_BASE 0xf1fc0000
534 #define MB86R0x_CCNT_BASE 0xfff42000
535 #define MB86R0x_CAN0_BASE 0xfff54000
536 #define MB86R0x_CAN1_BASE 0xfff55000
537 #define MB86R0x_I2C0_BASE 0xfff56000
538 #define MB86R0x_I2C1_BASE 0xfff57000
539 #define MB86R0x_EHCI_BASE 0xfff80000
540 #define MB86R0x_OHCI_BASE 0xfff81000
541 #define MB86R0x_IRC1_BASE 0xfffb0000
542 #define MB86R0x_MEMC_BASE 0xfffc0000
543 #define MB86R0x_TIMER_BASE 0xfffe0000
544 #define MB86R0x_UART0_BASE 0xfffe1000
545 #define MB86R0x_UART1_BASE 0xfffe2000
546 #define MB86R0x_IRCE_BASE 0xfffe4000
547 #define MB86R0x_CRG_BASE 0xfffe7000
548 #define MB86R0x_IRC0_BASE 0xfffe8000
549 #define MB86R0x_GPIO_BASE 0xfffe9000
550 #define MB86R0x_PWM0_BASE 0xfff41000
551 #define MB86R0x_PWM1_BASE 0xfff41100
553 #define MB86R0x_CRSR_SWRSTREQ (1 << 1)
556 * Timer register bits
558 #define MB86R0x_TIMER_ENABLE (1 << 7)
559 #define MB86R0x_TIMER_MODE_MSK (1 << 6)
560 #define MB86R0x_TIMER_MODE_FR (0 << 6)
561 #define MB86R0x_TIMER_MODE_PD (1 << 6)
563 #define MB86R0x_TIMER_INT_EN (1 << 5)
564 #define MB86R0x_TIMER_PRS_MSK (3 << 2)
565 #define MB86R0x_TIMER_PRS_4S (1 << 2)
566 #define MB86R0x_TIMER_PRS_8S (1 << 3)
567 #define MB86R0x_TIMER_SIZE_32 (1 << 1)
568 #define MB86R0x_TIMER_ONE_SHT (1 << 0)
571 * Clock reset generator bits
573 #define MB86R0x_CRG_CRPR_PLLRDY (1 << 8)
574 #define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0)
575 #define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0)
576 #define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0)
577 #define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0)
578 #define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0)
579 #define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0)
580 #define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0)
581 #define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0)
582 #define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0)
583 #define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0)
584 #define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0)
585 #define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0)
586 #define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0)
588 * DDR2 controller bits
590 #define MB86R0x_DDR2_DRCI_DRINI (1 << 15)
591 #define MB86R0x_DDR2_DRCI_CKEN (1 << 14)
592 #define MB86R0x_DDR2_DRCI_DRCMD (1 << 0)
593 #define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \
594 MB86R0x_DDR2_DRCI_CKEN | \
595 MB86R0x_DDR2_DRCI_DRCMD)
596 #define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \
597 MB86R0x_DDR2_DRCI_CKEN)
598 #define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN
599 #endif /* MB86R0X_H */