6 * Author : Carsten Schneider, mycable GmbH
10 * Matthias Weisser <weisserm@arcor.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
59 /* The mb86r0x chip control (CCNT) register set. */
85 /* The mb86r0x clock reset generator */
100 /* The mb86r0x timer */
101 struct mb86r0x_timer {
111 /* mb86r0x gdc display controller */
112 struct mb86r0x_gdc_dsp {
113 /* Display settings */
199 /* Display settings */
205 /* Layer 0 extended */
213 /* Layer 1 extended */
221 /* Layer 2 extended */
229 /* Layer 3 extended */
237 /* Layer 4 extended */
245 /* Layer 5 extended */
253 /* Multi screen control */
267 /* Extended transparency control */
276 /* YUV coefficients */
301 /* mb86r0x gdc capture controller */
302 struct mb86r0x_gdc_cap {
338 uint32_t pad08[12 + 1984];
341 /* mb86r0x gdc draw */
342 struct mb86r0x_gdc_draw {
459 /* mb86r0x gdc geometry engine */
460 struct mb86r0x_gdc_geom {
485 uint32_t pad04[16*1024 - 19];
486 struct mb86r0x_gdc_dsp dsp0;
487 struct mb86r0x_gdc_dsp dsp1;
488 uint32_t pad05[4*1024 - 2];
491 struct mb86r0x_gdc_cap cap0;
492 struct mb86r0x_gdc_cap cap1;
493 uint32_t pad06[4*1024];
494 uint32_t texture_base[16*1024];
495 struct mb86r0x_gdc_draw draw;
496 uint32_t pad07[7*1024];
497 struct mb86r0x_gdc_geom geom;
498 uint32_t pad08[7*1024];
501 #endif /* __ASSEMBLY__ */
504 * Physical Address Defines
506 #define MB86R0x_DDR2_BASE 0xf3000000
507 #define MB86R0x_GDC_BASE 0xf1fc0000
508 #define MB86R0x_CCNT_BASE 0xfff42000
509 #define MB86R0x_CAN0_BASE 0xfff54000
510 #define MB86R0x_CAN1_BASE 0xfff55000
511 #define MB86R0x_I2C0_BASE 0xfff56000
512 #define MB86R0x_I2C1_BASE 0xfff57000
513 #define MB86R0x_EHCI_BASE 0xfff80000
514 #define MB86R0x_OHCI_BASE 0xfff81000
515 #define MB86R0x_IRC1_BASE 0xfffb0000
516 #define MB86R0x_MEMC_BASE 0xfffc0000
517 #define MB86R0x_TIMER_BASE 0xfffe0000
518 #define MB86R0x_UART0_BASE 0xfffe1000
519 #define MB86R0x_UART1_BASE 0xfffe2000
520 #define MB86R0x_IRCE_BASE 0xfffe4000
521 #define MB86R0x_CRG_BASE 0xfffe7000
522 #define MB86R0x_IRC0_BASE 0xfffe8000
523 #define MB86R0x_GPIO_BASE 0xfffe9000
524 #define MB86R0x_PWM0_BASE 0xfff41000
525 #define MB86R0x_PWM1_BASE 0xfff41100
527 #define MB86R0x_CRSR_SWRSTREQ (1 << 1)
530 * Timer register bits
532 #define MB86R0x_TIMER_ENABLE (1 << 7)
533 #define MB86R0x_TIMER_MODE_MSK (1 << 6)
534 #define MB86R0x_TIMER_MODE_FR (0 << 6)
535 #define MB86R0x_TIMER_MODE_PD (1 << 6)
537 #define MB86R0x_TIMER_INT_EN (1 << 5)
538 #define MB86R0x_TIMER_PRS_MSK (3 << 2)
539 #define MB86R0x_TIMER_PRS_4S (1 << 2)
540 #define MB86R0x_TIMER_PRS_8S (1 << 3)
541 #define MB86R0x_TIMER_SIZE_32 (1 << 1)
542 #define MB86R0x_TIMER_ONE_SHT (1 << 0)
545 * Clock reset generator bits
547 #define MB86R0x_CRG_CRPR_PLLRDY (1 << 8)
548 #define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0)
549 #define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0)
550 #define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0)
551 #define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0)
552 #define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0)
553 #define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0)
554 #define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0)
555 #define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0)
556 #define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0)
557 #define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0)
558 #define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0)
559 #define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0)
560 #define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0)
562 * DDR2 controller bits
564 #define MB86R0x_DDR2_DRCI_DRINI (1 << 15)
565 #define MB86R0x_DDR2_DRCI_CKEN (1 << 14)
566 #define MB86R0x_DDR2_DRCI_DRCMD (1 << 0)
567 #define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \
568 MB86R0x_DDR2_DRCI_CKEN | \
569 MB86R0x_DDR2_DRCI_DRCMD)
570 #define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \
571 MB86R0x_DDR2_DRCI_CKEN)
572 #define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN
573 #endif /* MB86R0X_H */