2 * Copyright 2014, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV7_LS102XA_CONFIG_
8 #define _ASM_ARMV7_LS102XA_CONFIG_
10 #define CONFIG_SYS_CACHELINE_SIZE 64
12 #define OCRAM_BASE_ADDR 0x10000000
13 #define OCRAM_SIZE 0x00020000
15 #define CONFIG_SYS_IMMR 0x01000000
16 #define CONFIG_SYS_DCSRBAR 0x20000000
18 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
20 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
21 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
22 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
23 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
24 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
25 #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
26 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
27 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
28 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
29 #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
30 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
31 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
32 #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
33 #define CONFIG_SYS_LS102XA_USB1_ADDR \
34 (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
36 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
37 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
38 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
39 #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
40 #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
42 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
43 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
45 #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
47 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
48 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
49 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
51 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
53 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
54 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
56 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
58 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
59 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
62 #define CONFIG_SYS_FSL_DDR_BE
63 #define CONFIG_VERY_BIG_RAM
64 #ifdef CONFIG_SYS_FSL_DDR4
65 #define CONFIG_SYS_FSL_DDRC_GEN4
67 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3
69 #define CONFIG_SYS_FSL_DDR
70 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
71 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
74 #define CONFIG_SYS_FSL_IFC_BE
75 #define CONFIG_SYS_FSL_ESDHC_BE
76 #define CONFIG_SYS_FSL_WDOG_BE
77 #define CONFIG_SYS_FSL_DSPI_BE
78 #define CONFIG_SYS_FSL_QSPI_BE
79 #define CONFIG_SYS_FSL_DCU_BE
80 #define CONFIG_SYS_FSL_SEC_LE
82 #define DCU_LAYER_MAX_NUM 16
84 #define QE_MURAM_SIZE 0x6000UL
86 #define QE_NUM_OF_SNUM 28
88 #define CONFIG_SYS_FSL_SRDS_1
91 #define CONFIG_MAX_CPUS 2
92 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
93 #define CONFIG_NUM_DDR_CONTROLLERS 1
94 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
95 #define CONFIG_SYS_FSL_SEC_COMPAT 5
96 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
98 #error SoC not defined
101 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */