2 * Copyright 2014, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV7_LS102XA_CONFIG_
8 #define _ASM_ARMV7_LS102XA_CONFIG_
10 #define CONFIG_SYS_CACHELINE_SIZE 64
12 #define OCRAM_BASE_ADDR 0x10000000
13 #define OCRAM_SIZE 0x00020000
15 #define CONFIG_SYS_IMMR 0x01000000
17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
18 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
19 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
21 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
22 #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
23 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
24 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
25 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
26 #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
27 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
28 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
29 #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
30 #define CONFIG_SYS_LS102XA_USB1_ADDR \
31 (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
33 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
34 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
35 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
36 #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
37 #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
39 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
40 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
42 #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
44 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
45 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
46 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
48 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
50 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
51 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
53 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
56 #define CONFIG_SYS_FSL_DDR_BE
57 #define CONFIG_VERY_BIG_RAM
58 #ifdef CONFIG_SYS_FSL_DDR4
59 #define CONFIG_SYS_FSL_DDRC_GEN4
61 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3
63 #define CONFIG_SYS_FSL_DDR
64 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
65 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
68 #define CONFIG_SYS_FSL_IFC_BE
69 #define CONFIG_SYS_FSL_ESDHC_BE
70 #define CONFIG_SYS_FSL_WDOG_BE
71 #define CONFIG_SYS_FSL_DSPI_BE
72 #define CONFIG_SYS_FSL_QSPI_BE
73 #define CONFIG_SYS_FSL_DCU_BE
74 #define CONFIG_SYS_FSL_SEC_LE
76 #define DCU_LAYER_MAX_NUM 16
78 #define QE_MURAM_SIZE 0x6000UL
80 #define QE_NUM_OF_SNUM 28
82 #define CONFIG_SYS_FSL_SRDS_1
85 #define CONFIG_MAX_CPUS 2
86 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
87 #define CONFIG_NUM_DDR_CONTROLLERS 1
88 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
89 #define CONFIG_SYS_FSL_SEC_COMPAT 5
90 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
92 #error SoC not defined
95 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */