67a43117f90f57a00db351cf87b9dcfab02f531a
[oweals/u-boot.git] / arch / arm / include / asm / arch-ls102xa / config.h
1 /*
2  * Copyright 2014, Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef _ASM_ARMV7_LS102XA_CONFIG_
8 #define _ASM_ARMV7_LS102XA_CONFIG_
9
10 #define CONFIG_SYS_CACHELINE_SIZE               64
11
12 #define OCRAM_BASE_ADDR                         0x10000000
13 #define OCRAM_SIZE                              0x00020000
14 #define OCRAM_BASE_S_ADDR                       0x10010000
15 #define OCRAM_S_SIZE                            0x00010000
16
17 #define CONFIG_SYS_IMMR                         0x01000000
18 #define CONFIG_SYS_DCSRBAR                      0x20000000
19
20 #define CONFIG_SYS_DCSR_DCFG_ADDR       (CONFIG_SYS_DCSRBAR + 0x00220000)
21
22 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
23 #define CONFIG_SYS_CCI400_ADDR                  (CONFIG_SYS_IMMR + 0x00180000)
24 #define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
25 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x00530000)
26 #define CONFIG_SYS_FSL_ESDHC_ADDR               (CONFIG_SYS_IMMR + 0x00560000)
27 #define CONFIG_SYS_FSL_SCFG_ADDR                (CONFIG_SYS_IMMR + 0x00570000)
28 #define CONFIG_SYS_FSL_SEC_ADDR                 (CONFIG_SYS_IMMR + 0x700000)
29 #define CONFIG_SYS_FSL_JR0_ADDR                 (CONFIG_SYS_IMMR + 0x710000)
30 #define CONFIG_SYS_SEC_MON_ADDR                 (CONFIG_SYS_IMMR + 0x00e90000)
31 #define CONFIG_SYS_SFP_ADDR                     (CONFIG_SYS_IMMR + 0x00e80200)
32 #define CONFIG_SYS_FSL_SERDES_ADDR              (CONFIG_SYS_IMMR + 0x00ea0000)
33 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00ee0000)
34 #define CONFIG_SYS_FSL_LS1_CLK_ADDR             (CONFIG_SYS_IMMR + 0x00ee1000)
35 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011c0500)
36 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011d0500)
37 #define CONFIG_SYS_DCU_ADDR                     (CONFIG_SYS_IMMR + 0x01ce0000)
38 #define CONFIG_SYS_XHCI_USB1_ADDR               (CONFIG_SYS_IMMR + 0x02100000)
39 #define CONFIG_SYS_EHCI_USB1_ADDR               (CONFIG_SYS_IMMR + 0x07600000)
40
41 #define CONFIG_SYS_FSL_SEC_OFFSET               0x00700000
42 #define CONFIG_SYS_FSL_JR0_OFFSET               0x00710000
43 #define CONFIG_SYS_TSEC1_OFFSET                 0x01d10000
44 #define CONFIG_SYS_TSEC2_OFFSET                 0x01d50000
45 #define CONFIG_SYS_TSEC3_OFFSET                 0x01d90000
46 #define CONFIG_SYS_MDIO1_OFFSET                 0x01d24000
47
48 #define TSEC_BASE_ADDR  (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
49 #define MDIO_BASE_ADDR  (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
50
51 #define SCTR_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01b00000)
52
53 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01180000)
54 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01190000)
55 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x011a0000)
56
57 #define WDOG1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01ad0000)
58
59 #define QSPI0_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x00550000)
60 #define DSPI1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01100000)
61
62 #define LPUART_BASE                             (CONFIG_SYS_IMMR + 0x01950000)
63
64 #define CONFIG_SYS_PCIE1_ADDR                   (CONFIG_SYS_IMMR + 0x2400000)
65 #define CONFIG_SYS_PCIE2_ADDR                   (CONFIG_SYS_IMMR + 0x2500000)
66
67 #define CONFIG_SYS_PCIE1_PHYS_BASE              0x4000000000ULL
68 #define CONFIG_SYS_PCIE2_PHYS_BASE              0x4800000000ULL
69 #define CONFIG_SYS_PCIE1_VIRT_ADDR              0x24000000UL
70 #define CONFIG_SYS_PCIE2_VIRT_ADDR              0x34000000UL
71 #define CONFIG_SYS_PCIE_MMAP_SIZE               (192 * 1024 * 1024) /* 192M */
72 /*
73  * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
74  * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
75  */
76 #define CONFIG_SYS_PCIE1_PHYS_ADDR              (CONFIG_SYS_PCIE1_PHYS_BASE + \
77                                                  CONFIG_SYS_PCIE1_VIRT_ADDR)
78 #define CONFIG_SYS_PCIE2_PHYS_ADDR              (CONFIG_SYS_PCIE2_PHYS_BASE + \
79                                                  CONFIG_SYS_PCIE2_VIRT_ADDR)
80
81 /* SATA */
82 #define AHCI_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x02200000)
83 #define CONFIG_BOARD_LATE_INIT
84 #define CONFIG_SCSI
85 #define CONFIG_LIBATA
86 #define CONFIG_SCSI_AHCI
87 #define CONFIG_SCSI_AHCI_PLAT
88 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
89 #define CONFIG_SYS_SCSI_MAX_LUN         1
90 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
91                                                 CONFIG_SYS_SCSI_MAX_LUN)
92 #define CONFIG_DOS_PARTITION
93 #define CONFIG_SYS_FSL_ERRATUM_A008407
94
95 #ifdef CONFIG_DDR_SPD
96 #define CONFIG_SYS_FSL_DDR_BE
97 #define CONFIG_VERY_BIG_RAM
98 #ifdef CONFIG_SYS_FSL_DDR4
99 #define CONFIG_SYS_FSL_DDRC_GEN4
100 #else
101 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3
102 #endif
103 #define CONFIG_SYS_FSL_DDR
104 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE          ((phys_size_t)2 << 30)
105 #define CONFIG_MAX_MEM_MAPPED                   CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
106 #endif
107
108 #define CONFIG_SYS_FSL_IFC_BE
109 #define CONFIG_SYS_FSL_ESDHC_BE
110 #define CONFIG_SYS_FSL_WDOG_BE
111 #define CONFIG_SYS_FSL_DSPI_BE
112 #define CONFIG_SYS_FSL_QSPI_BE
113 #define CONFIG_SYS_FSL_DCU_BE
114 #define CONFIG_SYS_FSL_SEC_MON_LE
115 #define CONFIG_SYS_FSL_SEC_LE
116 #define CONFIG_SYS_FSL_SFP_VER_3_2
117 #define CONFIG_SYS_FSL_SFP_BE
118 #define CONFIG_SYS_FSL_SRK_LE
119
120 #define DCU_LAYER_MAX_NUM                       16
121
122 #define CONFIG_SYS_FSL_SRDS_1
123
124 #ifdef CONFIG_LS102XA
125 #define CONFIG_MAX_CPUS                         2
126 #define CONFIG_SYS_FSL_IFC_BANK_COUNT           8
127 #define CONFIG_NUM_DDR_CONTROLLERS              1
128 #define CONFIG_SYS_FSL_DDR_VER                  FSL_DDR_VER_5_0
129 #define CONFIG_SYS_FSL_SEC_COMPAT               5
130 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
131 #define CONFIG_SYS_FSL_ERRATUM_A008378
132 #define CONFIG_SYS_FSL_ERRATUM_A009663
133 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
134 #else
135 #error SoC not defined
136 #endif
137
138 #define FSL_IFC_COMPAT          "fsl,ifc"
139 #define FSL_QSPI_COMPAT         "fsl,ls1021a-qspi"
140 #define FSL_DSPI_COMPAT         "fsl,ls1021a-v1.0-dspi"
141
142 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */