2 * Keystone2: Common SoC definitions, structures etc.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARCH_HARDWARE_H
10 #define __ASM_ARCH_HARDWARE_H
16 #include <linux/sizes.h>
19 #define REG(addr) (*(volatile unsigned int *)(addr))
20 #define REG_P(addr) ((volatile unsigned int *)(addr))
22 typedef volatile unsigned int dv_reg;
23 typedef volatile unsigned int *dv_reg_p;
27 #define BIT(x) (1 << (x))
29 #define KS2_DDRPHY_PIR_OFFSET 0x04
30 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
31 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
32 #define KS2_DDRPHY_PGSR0_OFFSET 0x10
33 #define KS2_DDRPHY_PGSR1_OFFSET 0x14
34 #define KS2_DDRPHY_PLLCR_OFFSET 0x18
35 #define KS2_DDRPHY_PTR0_OFFSET 0x1C
36 #define KS2_DDRPHY_PTR1_OFFSET 0x20
37 #define KS2_DDRPHY_PTR2_OFFSET 0x24
38 #define KS2_DDRPHY_PTR3_OFFSET 0x28
39 #define KS2_DDRPHY_PTR4_OFFSET 0x2C
40 #define KS2_DDRPHY_DCR_OFFSET 0x44
42 #define KS2_DDRPHY_DTPR0_OFFSET 0x48
43 #define KS2_DDRPHY_DTPR1_OFFSET 0x4C
44 #define KS2_DDRPHY_DTPR2_OFFSET 0x50
46 #define KS2_DDRPHY_MR0_OFFSET 0x54
47 #define KS2_DDRPHY_MR1_OFFSET 0x58
48 #define KS2_DDRPHY_MR2_OFFSET 0x5C
49 #define KS2_DDRPHY_DTCR_OFFSET 0x68
50 #define KS2_DDRPHY_PGCR2_OFFSET 0x8C
52 #define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
53 #define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
54 #define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
55 #define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
57 #define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
59 #define IODDRM_MASK 0x00000180
60 #define ZCKSEL_MASK 0x01800000
61 #define CL_MASK 0x00000072
62 #define WR_MASK 0x00000E00
63 #define BL_MASK 0x00000003
64 #define RRMODE_MASK 0x00040000
65 #define UDIMM_MASK 0x20000000
66 #define BYTEMASK_MASK 0x0003FC00
67 #define MPRDQ_MASK 0x00000080
68 #define PDQ_MASK 0x00000070
69 #define NOSRA_MASK 0x08000000
70 #define ECC_MASK 0x00000001
72 /* DDR3 definitions */
73 #define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
74 #define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
75 #define KS2_DDR3A_DDRPHYC 0x02329000
77 #define KS2_DDR3_MIDR_OFFSET 0x00
78 #define KS2_DDR3_STATUS_OFFSET 0x04
79 #define KS2_DDR3_SDCFG_OFFSET 0x08
80 #define KS2_DDR3_SDRFC_OFFSET 0x10
81 #define KS2_DDR3_SDTIM1_OFFSET 0x18
82 #define KS2_DDR3_SDTIM2_OFFSET 0x1C
83 #define KS2_DDR3_SDTIM3_OFFSET 0x20
84 #define KS2_DDR3_SDTIM4_OFFSET 0x28
85 #define KS2_DDR3_PMCTL_OFFSET 0x38
86 #define KS2_DDR3_ZQCFG_OFFSET 0xC8
88 #define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
90 #define KS2_UART0_BASE 0x02530c00
91 #define KS2_UART1_BASE 0x02531000
94 #define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
95 #define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
96 #define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
99 #define KS2_PSC_BASE 0x02350000
100 #define KS2_LPSC_GEM_0 15
101 #define KS2_LPSC_TETRIS 52
102 #define KS2_TETRIS_PWR_DOMAIN 31
104 /* Chip configuration unlock codes and registers */
105 #define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
106 #define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
107 #define KS2_KICK0_MAGIC 0x83e70b13
108 #define KS2_KICK1_MAGIC 0x95a4f1e0
110 /* PLL control registers */
111 #define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
112 #define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
113 #define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
114 #define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
115 #define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
116 #define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
117 #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
118 #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
120 #define KS2_PLL_CNTRL_BASE 0x02310000
121 #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
122 #define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
123 #define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
124 #define KS2_RSTCTRL_KEY 0x5a69
125 #define KS2_RSTCTRL_MASK 0xffff0000
126 #define KS2_RSTCTRL_SWRST 0xfffe0000
129 #define KS2_SPI0_BASE 0x21000400
130 #define KS2_SPI1_BASE 0x21000600
131 #define KS2_SPI2_BASE 0x21000800
132 #define KS2_SPI_BASE KS2_SPI0_BASE
135 #define KS2_AEMIF_CNTRL_BASE 0x21000a00
136 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
138 /* Flag from ks2_debug options to check if DSPs need to stay ON */
139 #define DBG_LEAVE_DSPS_ON 0x1
142 #define KS2_QM_MANAGER_BASE 0x02a02000
143 #define KS2_QM_DESC_SETUP_BASE 0x02a03000
144 #define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
145 #define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
146 #define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
149 #define KS2_MSMC_CTRL_BASE 0x0bc00000
151 #ifdef CONFIG_SOC_K2HK
152 #include <asm/arch/hardware-k2hk.h>
155 #ifdef CONFIG_SOC_K2E
156 #include <asm/arch/hardware-k2e.h>
160 static inline int cpu_is_k2hk(void)
162 unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
163 unsigned int part_no = (jtag_id >> 12) & 0xffff;
165 return (part_no == 0xb981) ? 1 : 0;
168 static inline int cpu_is_k2e(void)
170 unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
171 unsigned int part_no = (jtag_id >> 12) & 0xffff;
173 return (part_no == 0xb9a6) ? 1 : 0;
176 static inline int cpu_revision(void)
178 unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
179 unsigned int rev = (jtag_id >> 28) & 0xf;
184 int cpu_to_bus(u32 *ptr, u32 length);
185 void sdelay(unsigned long);
189 #endif /* __ASM_ARCH_HARDWARE_H */