2 * Keystone2: Common SoC definitions, structures etc.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARCH_HARDWARE_H
10 #define __ASM_ARCH_HARDWARE_H
16 #include <linux/sizes.h>
19 #define REG(addr) (*(volatile unsigned int *)(addr))
20 #define REG_P(addr) ((volatile unsigned int *)(addr))
22 typedef volatile unsigned int dv_reg;
23 typedef volatile unsigned int *dv_reg_p;
25 #define ASYNC_EMIF_NUM_CS 4
26 #define ASYNC_EMIF_MODE_NOR 0
27 #define ASYNC_EMIF_MODE_NAND 1
28 #define ASYNC_EMIF_MODE_ONENAND 2
29 #define ASYNC_EMIF_PRESERVE -1
31 struct async_emif_config {
33 unsigned select_strobe;
49 void init_async_emif(int num_cs, struct async_emif_config *config);
51 struct ddr3_phy_config {
53 unsigned int pgcr1_mask;
54 unsigned int pgcr1_val;
60 unsigned int dcr_mask;
77 struct ddr3_emif_config {
89 #define BIT(x) (1 << (x))
91 #define KS2_DDRPHY_PIR_OFFSET 0x04
92 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
93 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
94 #define KS2_DDRPHY_PGSR0_OFFSET 0x10
95 #define KS2_DDRPHY_PGSR1_OFFSET 0x14
96 #define KS2_DDRPHY_PLLCR_OFFSET 0x18
97 #define KS2_DDRPHY_PTR0_OFFSET 0x1C
98 #define KS2_DDRPHY_PTR1_OFFSET 0x20
99 #define KS2_DDRPHY_PTR2_OFFSET 0x24
100 #define KS2_DDRPHY_PTR3_OFFSET 0x28
101 #define KS2_DDRPHY_PTR4_OFFSET 0x2C
102 #define KS2_DDRPHY_DCR_OFFSET 0x44
104 #define KS2_DDRPHY_DTPR0_OFFSET 0x48
105 #define KS2_DDRPHY_DTPR1_OFFSET 0x4C
106 #define KS2_DDRPHY_DTPR2_OFFSET 0x50
108 #define KS2_DDRPHY_MR0_OFFSET 0x54
109 #define KS2_DDRPHY_MR1_OFFSET 0x58
110 #define KS2_DDRPHY_MR2_OFFSET 0x5C
111 #define KS2_DDRPHY_DTCR_OFFSET 0x68
112 #define KS2_DDRPHY_PGCR2_OFFSET 0x8C
114 #define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
115 #define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
116 #define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
117 #define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
119 #define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
121 #define IODDRM_MASK 0x00000180
122 #define ZCKSEL_MASK 0x01800000
123 #define CL_MASK 0x00000072
124 #define WR_MASK 0x00000E00
125 #define BL_MASK 0x00000003
126 #define RRMODE_MASK 0x00040000
127 #define UDIMM_MASK 0x20000000
128 #define BYTEMASK_MASK 0x0003FC00
129 #define MPRDQ_MASK 0x00000080
130 #define PDQ_MASK 0x00000070
131 #define NOSRA_MASK 0x08000000
132 #define ECC_MASK 0x00000001
134 #define KS2_DDR3_MIDR_OFFSET 0x00
135 #define KS2_DDR3_STATUS_OFFSET 0x04
136 #define KS2_DDR3_SDCFG_OFFSET 0x08
137 #define KS2_DDR3_SDRFC_OFFSET 0x10
138 #define KS2_DDR3_SDTIM1_OFFSET 0x18
139 #define KS2_DDR3_SDTIM2_OFFSET 0x1C
140 #define KS2_DDR3_SDTIM3_OFFSET 0x20
141 #define KS2_DDR3_SDTIM4_OFFSET 0x28
142 #define KS2_DDR3_PMCTL_OFFSET 0x38
143 #define KS2_DDR3_ZQCFG_OFFSET 0xC8
145 #ifdef CONFIG_SOC_K2HK
146 #include <asm/arch/hardware-k2hk.h>
150 static inline int cpu_is_k2hk(void)
152 unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
153 unsigned int part_no = (jtag_id >> 12) & 0xffff;
155 return (part_no == 0xb981) ? 1 : 0;
158 static inline int cpu_revision(void)
160 unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
161 unsigned int rev = (jtag_id >> 28) & 0xf;
166 void share_all_segments(int priv_id);
167 int cpu_to_bus(u32 *ptr, u32 length);
168 void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
169 void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
170 void init_ddr3(void);
171 void sdelay(unsigned long);
175 #endif /* __ASM_ARCH_HARDWARE_H */