2 * K2HK: SoC definitions
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
10 #define __ASM_ARCH_HARDWARE_K2HK_H
12 #define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
13 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
14 #define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
15 #define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
16 #define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
17 #define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
19 #define K2HK_PLL_CNTRL_BASE 0x02310000
20 #define CLOCK_BASE K2HK_PLL_CNTRL_BASE
21 #define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
22 #define KS2_RSTCTRL_KEY 0x5a69
23 #define KS2_RSTCTRL_MASK 0xffff0000
24 #define KS2_RSTCTRL_SWRST 0xfffe0000
26 #define K2HK_PSC_BASE 0x02350000
27 #define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
28 #define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
29 #define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
31 #define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
33 #define ARM_PLL_EN BIT(13)
35 #define K2HK_SPI0_BASE 0x21000400
36 #define K2HK_SPI1_BASE 0x21000600
37 #define K2HK_SPI2_BASE 0x21000800
38 #define K2HK_SPI_BASE K2HK_SPI0_BASE
40 /* Chip configuration unlock codes and registers */
41 #define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
42 #define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
43 #define KEYSTONE_KICK0_MAGIC 0x83e70b13
44 #define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
47 #define KS2_PASS_BASE 0x02000000
49 /* PLL control registers */
50 #define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
51 #define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
52 #define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
53 #define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
54 #define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
55 #define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
56 #define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
57 #define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
58 #define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
59 #define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
61 /* Power and Sleep Controller (PSC) Domains */
62 #define K2HK_LPSC_MOD 0
63 #define K2HK_LPSC_DUMMY1 1
64 #define K2HK_LPSC_USB 2
65 #define K2HK_LPSC_EMIF25_SPI 3
66 #define K2HK_LPSC_TSIP 4
67 #define K2HK_LPSC_DEBUGSS_TRC 5
68 #define K2HK_LPSC_TETB_TRC 6
69 #define K2HK_LPSC_PKTPROC 7
70 #define KS2_LPSC_PA K2HK_LPSC_PKTPROC
71 #define K2HK_LPSC_SGMII 8
72 #define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
73 #define K2HK_LPSC_CRYPTO 9
74 #define K2HK_LPSC_PCIE 10
75 #define K2HK_LPSC_SRIO 11
76 #define K2HK_LPSC_VUSR0 12
77 #define K2HK_LPSC_CHIP_SRSS 13
78 #define K2HK_LPSC_MSMC 14
79 #define K2HK_LPSC_GEM_0 15
80 #define K2HK_LPSC_GEM_1 16
81 #define K2HK_LPSC_GEM_2 17
82 #define K2HK_LPSC_GEM_3 18
83 #define K2HK_LPSC_GEM_4 19
84 #define K2HK_LPSC_GEM_5 20
85 #define K2HK_LPSC_GEM_6 21
86 #define K2HK_LPSC_GEM_7 22
87 #define K2HK_LPSC_EMIF4F_DDR3A 23
88 #define K2HK_LPSC_EMIF4F_DDR3B 24
89 #define K2HK_LPSC_TAC 25
90 #define K2HK_LPSC_RAC 26
91 #define K2HK_LPSC_RAC_1 27
92 #define K2HK_LPSC_FFTC_A 28
93 #define K2HK_LPSC_FFTC_B 29
94 #define K2HK_LPSC_FFTC_C 30
95 #define K2HK_LPSC_FFTC_D 31
96 #define K2HK_LPSC_FFTC_E 32
97 #define K2HK_LPSC_FFTC_F 33
98 #define K2HK_LPSC_AI2 34
99 #define K2HK_LPSC_TCP3D_0 35
100 #define K2HK_LPSC_TCP3D_1 36
101 #define K2HK_LPSC_TCP3D_2 37
102 #define K2HK_LPSC_TCP3D_3 38
103 #define K2HK_LPSC_VCP2X4_A 39
104 #define K2HK_LPSC_CP2X4_B 40
105 #define K2HK_LPSC_VCP2X4_C 41
106 #define K2HK_LPSC_VCP2X4_D 42
107 #define K2HK_LPSC_VCP2X4_E 43
108 #define K2HK_LPSC_VCP2X4_F 44
109 #define K2HK_LPSC_VCP2X4_G 45
110 #define K2HK_LPSC_VCP2X4_H 46
111 #define K2HK_LPSC_BCP 47
112 #define K2HK_LPSC_DXB 48
113 #define K2HK_LPSC_VUSR1 49
114 #define K2HK_LPSC_XGE 50
115 #define K2HK_LPSC_ARM_SREFLEX 51
116 #define K2HK_LPSC_TETRIS 52
118 #define K2HK_UART0_BASE 0x02530c00
120 /* DDR3A definitions */
121 #define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
122 #define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
123 #define K2HK_DDR3A_DDRPHYC 0x02329000
124 /* DDR3B definitions */
125 #define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
126 #define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
127 #define K2HK_DDR3B_DDRPHYC 0x02328000
130 #define DEVICE_QM_MANAGER_BASE 0x02a02000
131 #define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
132 #define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
133 #define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
134 #define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
135 #define DEVICE_QM_NUM_LINKRAMS 2
136 #define DEVICE_QM_NUM_MEMREGIONS 20
138 #define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
139 #define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
140 #define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
141 #define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
143 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
144 #define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
145 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
148 #define K2HK_MSMC_CTRL_BASE 0x0bc00000
150 #endif /* __ASM_ARCH_HARDWARE_H */