2 * K2HK: SoC definitions
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
11 #define __ASM_ARCH_HARDWARE_K2HK_H
13 #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
15 #define KS2_ARM_PLL_EN BIT(13)
18 #define KS2_PASS_BASE 0x02000000
20 /* PLL control registers */
21 #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
22 #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
24 /* Power and Sleep Controller (PSC) Domains */
25 #define KS2_LPSC_MOD 0
26 #define KS2_LPSC_DUMMY1 1
27 #define KS2_LPSC_USB 2
28 #define KS2_LPSC_EMIF25_SPI 3
29 #define KS2_LPSC_TSIP 4
30 #define KS2_LPSC_DEBUGSS_TRC 5
31 #define KS2_LPSC_TETB_TRC 6
32 #define KS2_LPSC_PKTPROC 7
33 #define KS2_LPSC_PA KS2_LPSC_PKTPROC
34 #define KS2_LPSC_SGMII 8
35 #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
36 #define KS2_LPSC_CRYPTO 9
37 #define KS2_LPSC_PCIE 10
38 #define KS2_LPSC_SRIO 11
39 #define KS2_LPSC_VUSR0 12
40 #define KS2_LPSC_CHIP_SRSS 13
41 #define KS2_LPSC_MSMC 14
42 #define KS2_LPSC_GEM_1 16
43 #define KS2_LPSC_GEM_2 17
44 #define KS2_LPSC_GEM_3 18
45 #define KS2_LPSC_GEM_4 19
46 #define KS2_LPSC_GEM_5 20
47 #define KS2_LPSC_GEM_6 21
48 #define KS2_LPSC_GEM_7 22
49 #define KS2_LPSC_EMIF4F_DDR3A 23
50 #define KS2_LPSC_EMIF4F_DDR3B 24
51 #define KS2_LPSC_TAC 25
52 #define KS2_LPSC_RAC 26
53 #define KS2_LPSC_RAC_1 27
54 #define KS2_LPSC_FFTC_A 28
55 #define KS2_LPSC_FFTC_B 29
56 #define KS2_LPSC_FFTC_C 30
57 #define KS2_LPSC_FFTC_D 31
58 #define KS2_LPSC_FFTC_E 32
59 #define KS2_LPSC_FFTC_F 33
60 #define KS2_LPSC_AI2 34
61 #define KS2_LPSC_TCP3D_0 35
62 #define KS2_LPSC_TCP3D_1 36
63 #define KS2_LPSC_TCP3D_2 37
64 #define KS2_LPSC_TCP3D_3 38
65 #define KS2_LPSC_VCP2X4_A 39
66 #define KS2_LPSC_CP2X4_B 40
67 #define KS2_LPSC_VCP2X4_C 41
68 #define KS2_LPSC_VCP2X4_D 42
69 #define KS2_LPSC_VCP2X4_E 43
70 #define KS2_LPSC_VCP2X4_F 44
71 #define KS2_LPSC_VCP2X4_G 45
72 #define KS2_LPSC_VCP2X4_H 46
73 #define KS2_LPSC_BCP 47
74 #define KS2_LPSC_DXB 48
75 #define KS2_LPSC_VUSR1 49
76 #define KS2_LPSC_XGE 50
77 #define KS2_LPSC_ARM_SREFLEX 51
79 /* DDR3B definitions */
80 #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
81 #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
82 #define KS2_DDR3B_DDRPHYC 0x02328000
84 /* Number of DSP cores */
85 #define KS2_NUM_DSPS 8
87 #endif /* __ASM_ARCH_HARDWARE_H */