2 * K2HK: Clock management APIs
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __ASM_ARCH_CLOCK_K2HK_H
11 #define __ASM_ARCH_CLOCK_K2HK_H
26 ext_clk_count /* number of external clocks */
29 extern unsigned int external_clk[ext_clk_count];
55 #define KS2_CLK1_6 sys_clk0_6_clk
66 #define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
67 #define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
68 #define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
69 #define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
70 #define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
71 #define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
72 #define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
73 #define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
74 #define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
75 #define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
76 #define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
77 #define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
78 #define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
79 #define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
80 #define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
81 #define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
82 #define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
83 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
84 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
85 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
86 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}