3 * (C) Copyright 2004 eslab.whut.edu.cn
4 * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 struct pci_controller;
32 extern void pci_ixp_init(struct pci_controller *hose);
35 #define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
37 #define PCI_NP_CBE_BESL (4)
38 #define PCI_NP_AD_FUNCSL (8)
40 /*Register addressing definitions for PCI controller configuration
41 and status registers*/
43 #define PCI_CSR_BASE (0xC0000000)
45 #define PCI_NP_AD_OFFSET (0x00)
46 #define PCI_NP_CBE_OFFSET (0x04)
47 #define PCI_NP_WDATA_OFFSET (0x08)
48 #define PCI_NP_RDATA_OFFSET (0x0C)
49 #define PCI_CRP_OFFSET (0x10)
50 #define PCI_CRP_WDATA_OFFSET (0x14)
51 #define PCI_CRP_RDATA_OFFSET (0x18)
52 #define PCI_CSR_OFFSET (0x1C)
53 #define PCI_ISR_OFFSET (0x20)
54 #define PCI_INTEN_OFFSET (0x24)
55 #define PCI_DMACTRL_OFFSET (0x28)
56 #define PCI_AHBMEMBASE_OFFSET (0x2C)
57 #define PCI_AHBIOBASE_OFFSET (0x30)
58 #define PCI_PCIMEMBASE_OFFSET (0x34)
59 #define PCI_AHBDOORBELL_OFFSET (0x38)
60 #define PCI_PCIDOORBELL_OFFSET (0x3C)
61 #define PCI_ATPDMA0_AHBADDR (0x40)
62 #define PCI_ATPDMA0_PCIADDR (0x44)
63 #define PCI_ATPDMA0_LENADDR (0x48)
64 #define PCI_ATPDMA1_AHBADDR (0x4C)
65 #define PCI_ATPDMA1_PCIADDR (0x50)
66 #define PCI_ATPDMA1_LENADDR (0x54)
67 #define PCI_PTADMA0_AHBADDR (0x58)
68 #define PCI_PTADMA0_PCIADDR (0x5C)
69 #define PCI_PTADMA0_LENADDR (0x60)
70 #define PCI_PTADMA1_AHBADDR (0x64)
71 #define PCI_PTADMA1_PCIADDR (0x68)
72 #define PCI_PTADMA1_LENADDR (0x6C)
74 /*Non prefetch registers bit definitions*/
76 #define NP_CMD_INTACK (0x0)
77 #define NP_CMD_SPECIAL (0x1)
78 #define NP_CMD_IOREAD (0x2)
79 #define NP_CMD_IOWRITE (0x3)
80 #define NP_CMD_MEMREAD (0x6)
81 #define NP_CMD_MEMWRITE (0x7)
82 #define NP_CMD_CONFIGREAD (0xa)
83 #define NP_CMD_CONFIGWRITE (0xb)
86 /*Configuration Port register bit definitions*/
87 #define PCI_CRP_WRITE BIT(16)
89 /*ISR (Interrupt status) Register bit definitions*/
90 #define PCI_ISR_PSE BIT(0)
91 #define PCI_ISR_PFE BIT(1)
92 #define PCI_ISR_PPE BIT(2)
93 #define PCI_ISR_AHBE BIT(3)
94 #define PCI_ISR_APDC BIT(4)
95 #define PCI_ISR_PADC BIT(5)
96 #define PCI_ISR_ADB BIT(6)
97 #define PCI_ISR_PDB BIT(7)
99 /*INTEN (Interrupt Enable) Register bit definitions*/
100 #define PCI_INTEN_PSE BIT(0)
101 #define PCI_INTEN_PFE BIT(1)
102 #define PCI_INTEN_PPE BIT(2)
103 #define PCI_INTEN_AHBE BIT(3)
104 #define PCI_INTEN_APDC BIT(4)
105 #define PCI_INTEN_PADC BIT(5)
106 #define PCI_INTEN_ADB BIT(6)
107 #define PCI_INTEN_PDB BIT(7)
109 /*PCI configuration regs.*/
111 #define PCI_CFG_VENDOR_ID 0x00
112 #define PCI_CFG_DEVICE_ID 0x02
113 #define PCI_CFG_COMMAND 0x04
114 #define PCI_CFG_STATUS 0x06
115 #define PCI_CFG_REVISION 0x08
116 #define PCI_CFG_PROGRAMMING_IF 0x09
117 #define PCI_CFG_SUBCLASS 0x0a
118 #define PCI_CFG_CLASS 0x0b
119 #define PCI_CFG_CACHE_LINE_SIZE 0x0c
120 #define PCI_CFG_LATENCY_TIMER 0x0d
121 #define PCI_CFG_HEADER_TYPE 0x0e
122 #define PCI_CFG_BIST 0x0f
123 #define PCI_CFG_BASE_ADDRESS_0 0x10
124 #define PCI_CFG_BASE_ADDRESS_1 0x14
125 #define PCI_CFG_BASE_ADDRESS_2 0x18
126 #define PCI_CFG_BASE_ADDRESS_3 0x1c
127 #define PCI_CFG_BASE_ADDRESS_4 0x20
128 #define PCI_CFG_BASE_ADDRESS_5 0x24
129 #define PCI_CFG_CIS 0x28
130 #define PCI_CFG_SUB_VENDOR_ID 0x2c
131 #define PCI_CFG_SUB_SYSTEM_ID 0x2e
132 #define PCI_CFG_EXPANSION_ROM 0x30
133 #define PCI_CFG_RESERVED_0 0x34
134 #define PCI_CFG_RESERVED_1 0x38
135 #define PCI_CFG_DEV_INT_LINE 0x3c
136 #define PCI_CFG_DEV_INT_PIN 0x3d
137 #define PCI_CFG_MIN_GRANT 0x3e
138 #define PCI_CFG_MAX_LATENCY 0x3f
139 #define PCI_CFG_SPECIAL_USE 0x41
140 #define PCI_CFG_MODE 0x43
142 #define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
143 #define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
144 #define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
145 #define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
146 #define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
147 #define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
148 #define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
149 #define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
150 #define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
151 #define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
154 /*CSR Register bit definitions*/
155 #define PCI_CSR_HOST BIT(0)
156 #define PCI_CSR_ARBEN BIT(1)
157 #define PCI_CSR_ADS BIT(2)
158 #define PCI_CSR_PDS BIT(3)
159 #define PCI_CSR_ABE BIT(4)
160 #define PCI_CSR_DBT BIT(5)
161 #define PCI_CSR_ASE BIT(8)
162 #define PCI_CSR_IC BIT(15)
164 /*Configuration command bit definitions*/
165 #define PCI_CFG_CMD_IOAE BIT(0)
166 #define PCI_CFG_CMD_MAE BIT(1)
167 #define PCI_CFG_CMD_BME BIT(2)
168 #define PCI_CFG_CMD_MWIE BIT(4)
169 #define PCI_CFG_CMD_SER BIT(8)
170 #define PCI_CFG_CMD_FBBE BIT(9)
171 #define PCI_CFG_CMD_MDPE BIT(24)
172 #define PCI_CFG_CMD_STA BIT(27)
173 #define PCI_CFG_CMD_RTA BIT(28)
174 #define PCI_CFG_CMD_RMA BIT(29)
175 #define PCI_CFG_CMD_SSE BIT(30)
176 #define PCI_CFG_CMD_DPE BIT(31)
178 /*DMACTRL DMA Control and status Register*/
179 #define PCI_DMACTRL_APDCEN BIT(0)
180 #define PCI_DMACTRL_APDC0 BIT(4)
181 #define PCI_DMACTRL_APDE0 BIT(5)
182 #define PCI_DMACTRL_APDC1 BIT(6)
183 #define PCI_DMACTRL_APDE1 BIT(7)
184 #define PCI_DMACTRL_PADCEN BIT(8)
185 #define PCI_DMACTRL_PADC0 BIT(12)
186 #define PCI_DMACTRL_PADE0 BIT(13)
187 #define PCI_DMACTRL_PADC1 BIT(14)
188 #define PCI_DMACTRL_PADE1 BIT(15)