arch/arm/include/asm/arch-imx8m/imx-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017 NXP
   4  */
   5
   6 #ifndef __ASM_ARCH_IMX8M_REGS_H__
   7 #define __ASM_ARCH_IMX8M_REGS_H__
   8
   9 #define ARCH_MXC
  10
  11 #include <asm/mach-imx/regs-lcdif.h>
  12
  13 #define ROM_VERSION_A0          IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
  14 #define ROM_VERSION_B0          IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
  15
  16 #define M4_BOOTROM_BASE_ADDR   0x007E0000
  17
  18 #define GPIO1_BASE_ADDR         0X30200000
  19 #define GPIO2_BASE_ADDR         0x30210000
  20 #define GPIO3_BASE_ADDR         0x30220000
  21 #define GPIO4_BASE_ADDR         0x30230000
  22 #define GPIO5_BASE_ADDR         0x30240000
  23 #define WDOG1_BASE_ADDR         0x30280000
  24 #define WDOG2_BASE_ADDR         0x30290000
  25 #define WDOG3_BASE_ADDR         0x302A0000
  26 #define IOMUXC_BASE_ADDR        0x30330000
  27 #define IOMUXC_GPR_BASE_ADDR    0x30340000
  28 #define OCOTP_BASE_ADDR         0x30350000
  29 #define ANATOP_BASE_ADDR        0x30360000
  30 #define CCM_BASE_ADDR           0x30380000
  31 #define SRC_BASE_ADDR           0x30390000
  32 #define GPC_BASE_ADDR           0x303A0000
  33
  34 #define SYSCNT_RD_BASE_ADDR     0x306A0000
  35 #define SYSCNT_CMP_BASE_ADDR    0x306B0000
  36 #define SYSCNT_CTRL_BASE_ADDR   0x306C0000
  37
  38 #define UART1_BASE_ADDR         0x30860000
  39 #define UART3_BASE_ADDR         0x30880000
  40 #define UART2_BASE_ADDR         0x30890000
  41 #define I2C1_BASE_ADDR          0x30A20000
  42 #define I2C2_BASE_ADDR          0x30A30000
  43 #define I2C3_BASE_ADDR          0x30A40000
  44 #define I2C4_BASE_ADDR          0x30A50000
  45 #define UART4_BASE_ADDR         0x30A60000
  46 #define USDHC1_BASE_ADDR        0x30B40000
  47 #define USDHC2_BASE_ADDR        0x30B50000
  48 #ifdef CONFIG_IMX8MM
  49 #define USDHC3_BASE_ADDR        0x30B60000
  50 #endif
  51
  52 #define TZASC_BASE_ADDR         0x32F80000
  53
  54 #define MXS_LCDIF_BASE          IS_ENABLED(CONFIG_IMX8MQ) ? \
  55                                         0x30320000 : 0x32e00000
  56
  57 #define SRC_IPS_BASE_ADDR       0x30390000
  58 #define SRC_DDRC_RCR_ADDR       0x30391000
  59 #define SRC_DDRC2_RCR_ADDR      0x30391004
  60
  61 #define DDRC_DDR_SS_GPR0        0x3d000000
  62 #define DDRC_IPS_BASE_ADDR(X)   (0x3d400000 + ((X) * 0x2000000))
  63 #define DDR_CSD1_BASE_ADDR      0x40000000
  64
  65 #if !defined(__ASSEMBLY__)
  66 #include <asm/types.h>
  67 #include <linux/bitops.h>
  68 #include <stdbool.h>
  69
  70 #define GPR_TZASC_EN            BIT(0)
  71 #define GPR_TZASC_EN_LOCK       BIT(16)
  72
  73 #define SRC_SCR_M4_ENABLE_OFFSET        3
  74 #define SRC_SCR_M4_ENABLE_MASK          BIT(3)
  75 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
  76 #define SRC_SCR_M4C_NON_SCLR_RST_MASK   BIT(0)
  77 #define SRC_DDR1_ENABLE_MASK            0x8F000000UL
  78 #define SRC_DDR2_ENABLE_MASK            0x8F000000UL
  79 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
  80 #define SRC_DDR1_RCR_PHY_RESET_MASK     BIT(2)
  81 #define SRC_DDR1_RCR_CORE_RESET_N_MASK  BIT(1)
  82 #define SRC_DDR1_RCR_PRESET_N_MASK      BIT(0)
  83
  84 struct iomuxc_gpr_base_regs {
  85         u32 gpr[47];
  86 };
  87
  88 struct ocotp_regs {
  89         u32     ctrl;
  90         u32     ctrl_set;
  91         u32     ctrl_clr;
  92         u32     ctrl_tog;
  93         u32     timing;
  94         u32     rsvd0[3];
  95         u32     data;
  96         u32     rsvd1[3];
  97         u32     read_ctrl;
  98         u32     rsvd2[3];
  99         u32     read_fuse_data;
 100         u32     rsvd3[3];
 101         u32     sw_sticky;
 102         u32     rsvd4[3];
 103         u32     scs;
 104         u32     scs_set;
 105         u32     scs_clr;
 106         u32     scs_tog;
 107         u32     crc_addr;
 108         u32     rsvd5[3];
 109         u32     crc_value;
 110         u32     rsvd6[3];
 111         u32     version;
 112         u32     rsvd7[0xdb];
 113
 114         /* fuse banks */
 115         struct fuse_bank {
 116                 u32     fuse_regs[0x10];
 117         } bank[0];
 118 };
 119
 120 struct fuse_bank0_regs {
 121         u32 lock;
 122         u32 rsvd0[3];
 123         u32 uid_low;
 124         u32 rsvd1[3];
 125         u32 uid_high;
 126         u32 rsvd2[7];
 127 };
 128
 129 struct fuse_bank1_regs {
 130         u32 tester3;
 131         u32 rsvd0[3];
 132         u32 tester4;
 133         u32 rsvd1[3];
 134         u32 tester5;
 135         u32 rsvd2[3];
 136         u32 cfg0;
 137         u32 rsvd3[3];
 138 };
 139
 140 #ifdef CONFIG_IMX8MQ
 141 struct anamix_pll {
 142         u32 audio_pll1_cfg0;
 143         u32 audio_pll1_cfg1;
 144         u32 audio_pll2_cfg0;
 145         u32 audio_pll2_cfg1;
 146         u32 video_pll_cfg0;
 147         u32 video_pll_cfg1;
 148         u32 gpu_pll_cfg0;
 149         u32 gpu_pll_cfg1;
 150         u32 vpu_pll_cfg0;
 151         u32 vpu_pll_cfg1;
 152         u32 arm_pll_cfg0;
 153         u32 arm_pll_cfg1;
 154         u32 sys_pll1_cfg0;
 155         u32 sys_pll1_cfg1;
 156         u32 sys_pll1_cfg2;
 157         u32 sys_pll2_cfg0;
 158         u32 sys_pll2_cfg1;
 159         u32 sys_pll2_cfg2;
 160         u32 sys_pll3_cfg0;
 161         u32 sys_pll3_cfg1;
 162         u32 sys_pll3_cfg2;
 163         u32 video_pll2_cfg0;
 164         u32 video_pll2_cfg1;
 165         u32 video_pll2_cfg2;
 166         u32 dram_pll_cfg0;
 167         u32 dram_pll_cfg1;
 168         u32 dram_pll_cfg2;
 169         u32 digprog;
 170         u32 osc_misc_cfg;
 171         u32 pllout_monitor_cfg;
 172         u32 frac_pllout_div_cfg;
 173         u32 sscg_pllout_div_cfg;
 174 };
 175 #else
 176 struct anamix_pll {
 177         u32 audio_pll1_gnrl_ctl;
 178         u32 audio_pll1_fdiv_ctl0;
 179         u32 audio_pll1_fdiv_ctl1;
 180         u32 audio_pll1_sscg_ctl;
 181         u32 audio_pll1_mnit_ctl;
 182         u32 audio_pll2_gnrl_ctl;
 183         u32 audio_pll2_fdiv_ctl0;
 184         u32 audio_pll2_fdiv_ctl1;
 185         u32 audio_pll2_sscg_ctl;
 186         u32 audio_pll2_mnit_ctl;
 187         u32 video_pll1_gnrl_ctl;
 188         u32 video_pll1_fdiv_ctl0;
 189         u32 video_pll1_fdiv_ctl1;
 190         u32 video_pll1_sscg_ctl;
 191         u32 video_pll1_mnit_ctl;
 192         u32 reserved[5];
 193         u32 dram_pll_gnrl_ctl;
 194         u32 dram_pll_fdiv_ctl0;
 195         u32 dram_pll_fdiv_ctl1;
 196         u32 dram_pll_sscg_ctl;
 197         u32 dram_pll_mnit_ctl;
 198         u32 gpu_pll_gnrl_ctl;
 199         u32 gpu_pll_div_ctl;
 200         u32 gpu_pll_locked_ctl1;
 201         u32 gpu_pll_mnit_ctl;
 202         u32 vpu_pll_gnrl_ctl;
 203         u32 vpu_pll_div_ctl;
 204         u32 vpu_pll_locked_ctl1;
 205         u32 vpu_pll_mnit_ctl;
 206         u32 arm_pll_gnrl_ctl;
 207         u32 arm_pll_div_ctl;
 208         u32 arm_pll_locked_ctl1;
 209         u32 arm_pll_mnit_ctl;
 210         u32 sys_pll1_gnrl_ctl;
 211         u32 sys_pll1_div_ctl;
 212         u32 sys_pll1_locked_ctl1;
 213         u32 reserved2[24];
 214         u32 sys_pll1_mnit_ctl;
 215         u32 sys_pll2_gnrl_ctl;
 216         u32 sys_pll2_div_ctl;
 217         u32 sys_pll2_locked_ctl1;
 218         u32 sys_pll2_mnit_ctl;
 219         u32 sys_pll3_gnrl_ctl;
 220         u32 sys_pll3_div_ctl;
 221         u32 sys_pll3_locked_ctl1;
 222         u32 sys_pll3_mnit_ctl;
 223         u32 anamix_misc_ctl;
 224         u32 anamix_clk_mnit_ctl;
 225         u32 reserved3[437];
 226         u32 digprog;
 227 };
 228 #endif
 229
 230 struct fuse_bank9_regs {
 231         u32 mac_addr0;
 232         u32 rsvd0[3];
 233         u32 mac_addr1;
 234         u32 rsvd1[11];
 235 };
 236
 237 /* System Reset Controller (SRC) */
 238 struct src {
 239         u32 scr;
 240         u32 a53rcr;
 241         u32 a53rcr1;
 242         u32 m4rcr;
 243         u32 reserved1[4];
 244         u32 usbophy1_rcr;
 245         u32 usbophy2_rcr;
 246         u32 mipiphy_rcr;
 247         u32 pciephy_rcr;
 248         u32 hdmi_rcr;
 249         u32 disp_rcr;
 250         u32 reserved2[2];
 251         u32 gpu_rcr;
 252         u32 vpu_rcr;
 253         u32 pcie2_rcr;
 254         u32 mipiphy1_rcr;
 255         u32 mipiphy2_rcr;
 256         u32 reserved3;
 257         u32 sbmr1;
 258         u32 srsr;
 259         u32 reserved4[2];
 260         u32 sisr;
 261         u32 simr;
 262         u32 sbmr2;
 263         u32 gpr1;
 264         u32 gpr2;
 265         u32 gpr3;
 266         u32 gpr4;
 267         u32 gpr5;
 268         u32 gpr6;
 269         u32 gpr7;
 270         u32 gpr8;
 271         u32 gpr9;
 272         u32 gpr10;
 273         u32 reserved5[985];
 274         u32 ddr1_rcr;
 275         u32 ddr2_rcr;
 276 };
 277
 278 #define WDOG_WDT_MASK   BIT(3)
 279 #define WDOG_WDZST_MASK BIT(0)
 280 struct wdog_regs {
 281         u16     wcr;    /* Control */
 282         u16     wsr;    /* Service */
 283         u16     wrsr;   /* Reset Status */
 284         u16     wicr;   /* Interrupt Control */
 285         u16     wmcr;   /* Miscellaneous Control */
 286 };
 287
 288 struct bootrom_sw_info {
 289         u8 reserved_1;
 290         u8 boot_dev_instance;
 291         u8 boot_dev_type;
 292         u8 reserved_2;
 293         u32 core_freq;
 294         u32 axi_freq;
 295         u32 ddr_freq;
 296         u32 tick_freq;
 297         u32 reserved_3[3];
 298 };
 299
 300 #define ROM_SW_INFO_ADDR_B0     (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
 301                                  0x000009e8)
 302 #define ROM_SW_INFO_ADDR_A0     0x000009e8
 303
 304 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
 305                 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
 306                 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
 307 #endif
 308 #endif