1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2018-2019 NXP
5 * Peng Fan <peng.fan@nxp.com>
8 #ifndef _ASM_ARCH_IMX8MM_CLOCK_H
9 #define _ASM_ARCH_IMX8MM_CLOCK_H
12 #include <linux/bitops.h>
15 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
24 #define LOCK_STATUS BIT(31)
25 #define LOCK_SEL_MASK BIT(29)
26 #define CLKE_MASK BIT(13)
27 #define RST_MASK BIT(9)
28 #define BYPASS_MASK BIT(4)
30 #define MDIV_MASK GENMASK(21, 12)
32 #define PDIV_MASK GENMASK(9, 4)
34 #define SDIV_MASK GENMASK(2, 0)
36 #define KDIV_MASK GENMASK(15, 0)
38 struct imx_int_pll_rate_table {
64 GPU3D_CORE_CLK_ROOT = 3,
65 GPU3D_SHADER_CLK_ROOT = 4,
67 AUDIO_AXI_CLK_ROOT = 6,
68 HSIO_AXI_CLK_ROOT = 7,
69 MEDIA_ISP_CLK_ROOT = 8,
70 MAIN_AXI_CLK_ROOT = 16,
71 ENET_AXI_CLK_ROOT = 17,
72 NAND_USDHC_BUS_CLK_ROOT = 18,
73 VPU_BUS_CLK_ROOT = 19,
74 MEDIA_AXI_CLK_ROOT = 20,
75 MEDIA_APB_CLK_ROOT = 21,
76 HDMI_APB_CLK_ROOT = 22,
77 HDMI_AXI_CLK_ROOT = 23,
78 GPU_AXI_CLK_ROOT = 24,
79 GPU_AHB_CLK_ROOT = 25,
86 AUDIO_AHB_CLK_ROOT = 34,
87 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
88 MEDIA_DISP2_CLK_ROOT = 38,
91 DRAM_ALT_CLK_ROOT = 64,
92 DRAM_APB_CLK_ROOT = 65,
97 PCIE_PHY_CLK_ROOT = 71,
98 PCIE_AUX_CLK_ROOT = 72,
107 ENET_QOS_CLK_ROOT = 81,
108 ENET_QOS_TIMER_CLK_ROOT = 82,
109 ENET_REF_CLK_ROOT = 83,
110 ENET_TIMER_CLK_ROOT = 84,
111 ENET_PHY_REF_CLK_ROOT = 85,
114 USDHC1_CLK_ROOT = 88,
115 USDHC2_CLK_ROOT = 89,
124 USB_CORE_REF_CLK_ROOT = 98,
125 USB_PHY_REF_CLK_ROOT = 99,
127 ECSPI1_CLK_ROOT = 101,
128 ECSPI2_CLK_ROOT = 102,
139 TRACE_CLK_ROOT = 113,
141 WRCLK_CLK_ROOT = 115,
144 HDMI_FDCC_TST_CLK_ROOT = 118,
145 HDMI_27M_CLK_ROOT = 119,
146 HDMI_REF_266M_CLK_ROOT = 120,
147 USDHC3_CLK_ROOT = 121,
148 MEDIA_CAM1_PIX_CLK_ROOT = 122,
149 MEDIA_MIPI_PHY1_REF_CLK_ROOT = 123,
150 MEDIA_DISP1_PIX_CLK_ROOT = 124,
151 MEDIA_CAM2_PIX_CLK_ROOT = 125,
152 MEDIA_LDB_CLK_ROOT = 126,
153 MEMREPAIR_CLK_ROOT = 127,
154 MEDIA_MIPI_TEST_BYTE_CLK = 130,
155 ECSPI3_CLK_ROOT = 131,
157 VPU_VC8000E_CLK_ROOT = 133,
161 #elif defined(CONFIG_IMX8MN)
162 enum clk_root_index {
163 ARM_A53_CLK_ROOT = 0,
165 GPU_CORE_CLK_ROOT = 3,
166 GPU_SHADER_CLK_ROOT = 4,
167 MAIN_AXI_CLK_ROOT = 16,
168 ENET_AXI_CLK_ROOT = 17,
169 NAND_USDHC_BUS_CLK_ROOT = 18,
170 DISPLAY_AXI_CLK_ROOT = 20,
171 DISPLAY_APB_CLK_ROOT = 21,
172 USB_BUS_CLK_ROOT = 23,
173 GPU_AXI_CLK_ROOT = 24,
174 GPU_AHB_CLK_ROOT = 25,
178 AUDIO_AHB_CLK_ROOT = 34,
181 DRAM_ALT_CLK_ROOT = 64,
182 DRAM_APB_CLK_ROOT = 65,
183 DISPLAY_PIXEL_CLK_ROOT = 74,
188 SPDIF1_CLK_ROOT = 81,
189 ENET_REF_CLK_ROOT = 83,
190 ENET_TIMER_CLK_ROOT = 84,
191 ENET_PHY_REF_CLK_ROOT = 85,
194 USDHC1_CLK_ROOT = 88,
195 USDHC2_CLK_ROOT = 89,
204 USB_CORE_REF_CLK_ROOT = 98,
205 USB_PHY_REF_CLK_ROOT = 99,
207 ECSPI1_CLK_ROOT = 101,
208 ECSPI2_CLK_ROOT = 102,
219 TRACE_CLK_ROOT = 113,
221 WRCLK_CLK_ROOT = 115,
224 MIPI_DSI_CORE_CLK_ROOT = 118,
225 DISPLAY_DSI_PHY_REF_CLK_ROOT = 119,
226 MIPI_DSI_DBI_CLK_ROOT = 120,
227 USDHC3_CLK_ROOT = 121,
228 DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122,
229 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
230 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
231 MIPI_CSI2_ESC_CLK_ROOT = 127,
232 ECSPI3_CLK_ROOT = 131,
238 enum clk_root_index {
239 ARM_A53_CLK_ROOT = 0,
241 VPU_A53_CLK_ROOT = 2,
244 MAIN_AXI_CLK_ROOT = 16,
245 ENET_AXI_CLK_ROOT = 17,
246 NAND_USDHC_BUS_CLK_ROOT = 18,
247 VPU_BUS_CLK_ROOT = 19,
248 DISPLAY_AXI_CLK_ROOT = 20,
249 DISPLAY_APB_CLK_ROOT = 21,
250 DISPLAY_RTRM_CLK_ROOT = 22,
251 USB_BUS_CLK_ROOT = 23,
252 GPU_AXI_CLK_ROOT = 24,
253 GPU_AHB_CLK_ROOT = 25,
255 NOC_APB_CLK_ROOT = 27,
258 AUDIO_AHB_CLK_ROOT = 34,
259 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
262 DRAM_ALT_CLK_ROOT = 64,
263 DRAM_APB_CLK_ROOT = 65,
264 VPU_G1_CLK_ROOT = 66,
265 VPU_G2_CLK_ROOT = 67,
266 DISPLAY_DTRC_CLK_ROOT = 68,
267 DISPLAY_DC8000_CLK_ROOT = 69,
268 PCIE_CTRL_CLK_ROOT = 70,
269 PCIE_PHY_CLK_ROOT = 71,
270 PCIE_AUX_CLK_ROOT = 72,
271 DC_PIXEL_CLK_ROOT = 73,
272 LCDIF_PIXEL_CLK_ROOT = 74,
279 SPDIF1_CLK_ROOT = 81,
280 SPDIF2_CLK_ROOT = 82,
281 ENET_REF_CLK_ROOT = 83,
282 ENET_TIMER_CLK_ROOT = 84,
283 ENET_PHY_REF_CLK_ROOT = 85,
286 USDHC1_CLK_ROOT = 88,
287 USDHC2_CLK_ROOT = 89,
296 USB_CORE_REF_CLK_ROOT = 98,
297 USB_PHY_REF_CLK_ROOT = 99,
299 ECSPI1_CLK_ROOT = 101,
300 ECSPI2_CLK_ROOT = 102,
311 TRACE_CLK_ROOT = 113,
313 WRCLK_CLK_ROOT = 115,
316 MIPI_DSI_CORE_CLK_ROOT = 118,
317 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
318 MIPI_DSI_DBI_CLK_ROOT = 120,
319 USDHC3_CLK_ROOT = 121,
320 MIPI_CSI1_CORE_CLK_ROOT = 122,
321 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
322 MIPI_CSI1_ESC_CLK_ROOT = 124,
323 MIPI_CSI2_CORE_CLK_ROOT = 125,
324 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
325 MIPI_CSI2_ESC_CLK_ROOT = 127,
326 PCIE2_CTRL_CLK_ROOT = 128,
327 PCIE2_PHY_CLK_ROOT = 129,
328 PCIE2_AUX_CLK_ROOT = 130,
329 ECSPI3_CLK_ROOT = 131,
331 VPU_H1_CLK_ROOT = 133,
343 SYSTEM_PLL1_800M_CLK,
344 SYSTEM_PLL1_400M_CLK,
345 SYSTEM_PLL1_266M_CLK,
346 SYSTEM_PLL1_200M_CLK,
347 SYSTEM_PLL1_160M_CLK,
348 SYSTEM_PLL1_133M_CLK,
349 SYSTEM_PLL1_100M_CLK,
352 SYSTEM_PLL2_1000M_CLK,
353 SYSTEM_PLL2_500M_CLK,
354 SYSTEM_PLL2_333M_CLK,
355 SYSTEM_PLL2_250M_CLK,
356 SYSTEM_PLL2_200M_CLK,
357 SYSTEM_PLL2_166M_CLK,
358 SYSTEM_PLL2_125M_CLK,
359 SYSTEM_PLL2_100M_CLK,
374 enum clk_ccgr_index {
407 CCGR_SNVSMIX_IPG_CLK = 32,
420 CCGR_QOS_DISPMIX = 45,
421 CCGR_QOS_ETHENET = 46,
440 CCGR_IRQ_STEER_8MP = 63,
441 CCGR_SIM_DISPLAY = 63,
446 CCGR_SIM_WAKEUP = 68,
457 CCGR_USB_MSCALE_PL301 = 77,
458 CCGR_USB_PHY_8MP = 79,
476 CCGR_TEMP_SENSOR = 98,
477 CCGR_VPUMIX_BUS = 99,
484 CLK_SRC_CKIL_SYNC_REQ = 0,
485 CLK_SRC_ARM_PLL_EN = 1,
486 CLK_SRC_GPU_PLL_EN = 2,
487 CLK_SRC_VPU_PLL_EN = 3,
488 CLK_SRC_DRAM_PLL_EN = 4,
489 CLK_SRC_SYSTEM_PLL1_EN = 5,
490 CLK_SRC_SYSTEM_PLL2_EN = 6,
491 CLK_SRC_SYSTEM_PLL3_EN = 7,
492 CLK_SRC_AUDIO_PLL1_EN = 8,
493 CLK_SRC_AUDIO_PLL2_EN = 9,
494 CLK_SRC_VIDEO_PLL1_EN = 10,
495 CLK_SRC_RESERVED = 11,
496 CLK_SRC_ARM_PLL = 12,
497 CLK_SRC_GPU_PLL = 13,
498 CLK_SRC_VPU_PLL = 14,
499 CLK_SRC_DRAM_PLL = 15,
500 CLK_SRC_SYSTEM_PLL1_800M = 16,
501 CLK_SRC_SYSTEM_PLL1_400M = 17,
502 CLK_SRC_SYSTEM_PLL1_266M = 18,
503 CLK_SRC_SYSTEM_PLL1_200M = 19,
504 CLK_SRC_SYSTEM_PLL1_160M = 20,
505 CLK_SRC_SYSTEM_PLL1_133M = 21,
506 CLK_SRC_SYSTEM_PLL1_100M = 22,
507 CLK_SRC_SYSTEM_PLL1_80M = 23,
508 CLK_SRC_SYSTEM_PLL1_40M = 24,
509 CLK_SRC_SYSTEM_PLL2_1000M = 25,
510 CLK_SRC_SYSTEM_PLL2_500M = 26,
511 CLK_SRC_SYSTEM_PLL2_333M = 27,
512 CLK_SRC_SYSTEM_PLL2_250M = 28,
513 CLK_SRC_SYSTEM_PLL2_200M = 29,
514 CLK_SRC_SYSTEM_PLL2_166M = 30,
515 CLK_SRC_SYSTEM_PLL2_125M = 31,
516 CLK_SRC_SYSTEM_PLL2_100M = 32,
517 CLK_SRC_SYSTEM_PLL2_50M = 33,
518 CLK_SRC_SYSTEM_PLL3 = 34,
519 CLK_SRC_AUDIO_PLL1 = 35,
520 CLK_SRC_AUDIO_PLL2 = 36,
521 CLK_SRC_VIDEO_PLL1 = 37,
524 #define INTPLL_LOCK_MASK BIT(31)
525 #define INTPLL_LOCK_SEL_MASK BIT(29)
526 #define INTPLL_EXT_BYPASS_MASK BIT(28)
527 #define INTPLL_DIV20_CLKE_MASK BIT(27)
528 #define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
529 #define INTPLL_DIV10_CLKE_MASK BIT(25)
530 #define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
531 #define INTPLL_DIV8_CLKE_MASK BIT(23)
532 #define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
533 #define INTPLL_DIV6_CLKE_MASK BIT(21)
534 #define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
535 #define INTPLL_DIV5_CLKE_MASK BIT(19)
536 #define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
537 #define INTPLL_DIV4_CLKE_MASK BIT(17)
538 #define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
539 #define INTPLL_DIV3_CLKE_MASK BIT(15)
540 #define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
541 #define INTPLL_DIV2_CLKE_MASK BIT(13)
542 #define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
543 #define INTPLL_CLKE_MASK BIT(11)
544 #define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
545 #define INTPLL_RST_MASK BIT(9)
546 #define INTPLL_RST_OVERRIDE_MASK BIT(8)
547 #define INTPLL_BYPASS_MASK BIT(4)
548 #define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
549 #define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
551 #define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
552 #define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
553 #define INTPLL_MAIN_DIV_SHIFT 12
554 #define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
555 #define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
556 #define INTPLL_PRE_DIV_SHIFT 4
557 #define INTPLL_POST_DIV_MASK GENMASK(2, 0)
558 #define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
559 #define INTPLL_POST_DIV_SHIFT 0
561 #define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
562 #define INTPLL_LOCK_CON_DLY_SHIFT 4
563 #define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
564 #define INTPLL_LOCK_CON_OUT_SHIFT 2
565 #define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
566 #define INTPLL_LOCK_CON_IN_SHIFT 0
568 #define INTPLL_LRD_EN_MASK BIT(21)
569 #define INTPLL_FOUT_MASK BIT(20)
570 #define INTPLL_AFC_SEL_MASK BIT(19)
571 #define INTPLL_PBIAS_CTRL_MASK BIT(18)
572 #define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
573 #define INTPLL_AFCINIT_SEL_MASK BIT(16)
574 #define INTPLL_FSEL_MASK BIT(14)
575 #define INTPLL_FEED_EN_MASK BIT(13)
576 #define INTPLL_EXTAFC_MASK GENMASK(7, 3)
577 #define INTPLL_AFC_EN_MASK BIT(2)
578 #define INTPLL_ICP_MASK GENMASK(1, 0)