arch/arm/include/asm/arch-imx8m/clock_imx8mm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #ifndef _ASM_ARCH_IMX8MM_CLOCK_H
   9 #define _ASM_ARCH_IMX8MM_CLOCK_H
  10
  11 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k)                   \
  12         {                                                       \
  13                 .rate   =       (_rate),                        \
  14                 .mdiv   =       (_m),                           \
  15                 .pdiv   =       (_p),                           \
  16                 .sdiv   =       (_s),                           \
  17                 .kdiv   =       (_k),                           \
  18         }
  19
  20 #define LOCK_STATUS     BIT(31)
  21 #define LOCK_SEL_MASK   BIT(29)
  22 #define CLKE_MASK       BIT(13)
  23 #define RST_MASK        BIT(9)
  24 #define BYPASS_MASK     BIT(4)
  25 #define MDIV_SHIFT      12
  26 #define MDIV_MASK       GENMASK(21, 12)
  27 #define PDIV_SHIFT      4
  28 #define PDIV_MASK       GENMASK(9, 4)
  29 #define SDIV_SHIFT      0
  30 #define SDIV_MASK       GENMASK(2, 0)
  31 #define KDIV_SHIFT      0
  32 #define KDIV_MASK       GENMASK(15, 0)
  33
  34 struct imx_int_pll_rate_table {
  35         u32 rate;
  36         int mdiv;
  37         int pdiv;
  38         int sdiv;
  39         int kdiv;
  40 };
  41
  42 enum pll_clocks {
  43         ANATOP_ARM_PLL,
  44         ANATOP_VPU_PLL,
  45         ANATOP_GPU_PLL,
  46         ANATOP_SYSTEM_PLL1,
  47         ANATOP_SYSTEM_PLL2,
  48         ANATOP_SYSTEM_PLL3,
  49         ANATOP_AUDIO_PLL1,
  50         ANATOP_AUDIO_PLL2,
  51         ANATOP_VIDEO_PLL,
  52         ANATOP_DRAM_PLL,
  53 };
  54
  55 #ifdef CONFIG_IMX8MP
  56 enum clk_root_index {
  57         ARM_A53_CLK_ROOT                = 0,
  58         ARM_M7_CLK_ROOT                 = 1,
  59         ML_CLK_ROOT                     = 2,
  60         GPU3D_CORE_CLK_ROOT             = 3,
  61         GPU3D_SHADER_CLK_ROOT           = 4,
  62         GPU2D_CLK_ROOT                  = 5,
  63         AUDIO_AXI_CLK_ROOT              = 6,
  64         HSIO_AXI_CLK_ROOT               = 7,
  65         MEDIA_ISP_CLK_ROOT              = 8,
  66         MAIN_AXI_CLK_ROOT               = 16,
  67         ENET_AXI_CLK_ROOT               = 17,
  68         NAND_USDHC_BUS_CLK_ROOT         = 18,
  69         VPU_BUS_CLK_ROOT                = 19,
  70         MEDIA_AXI_CLK_ROOT              = 20,
  71         MEDIA_APB_CLK_ROOT              = 21,
  72         HDMI_APB_CLK_ROOT               = 22,
  73         HDMI_AXI_CLK_ROOT               = 23,
  74         GPU_AXI_CLK_ROOT                = 24,
  75         GPU_AHB_CLK_ROOT                = 25,
  76         NOC_CLK_ROOT                    = 26,
  77         NOC_IO_CLK_ROOT                 = 27,
  78         ML_AXI_CLK_ROOT                 = 28,
  79         ML_AHB_CLK_ROOT                 = 29,
  80         AHB_CLK_ROOT                    = 32,
  81         IPG_CLK_ROOT                    = 33,
  82         AUDIO_AHB_CLK_ROOT              = 34,
  83         MIPI_DSI_ESC_RX_CLK_ROOT        = 36,
  84         MEDIA_DISP2_CLK_ROOT            = 38,
  85         DRAM_SEL_CFG                    = 48,
  86         CORE_SEL_CFG                    = 49,
  87         DRAM_ALT_CLK_ROOT               = 64,
  88         DRAM_APB_CLK_ROOT               = 65,
  89         VPU_G1_CLK_ROOT                 = 66,
  90         VPU_G2_CLK_ROOT                 = 67,
  91         CAN1_CLK_ROOT                   = 68,
  92         CAN2_CLK_ROOT                   = 69,
  93         PCIE_PHY_CLK_ROOT               = 71,
  94         PCIE_AUX_CLK_ROOT               = 72,
  95         I2C5_CLK_ROOT                   = 73,
  96         I2C6_CLK_ROOT                   = 74,
  97         SAI1_CLK_ROOT                   = 75,
  98         SAI2_CLK_ROOT                   = 76,
  99         SAI3_CLK_ROOT                   = 77,
 100         SAI4_CLK_ROOT                   = 78,
 101         SAI5_CLK_ROOT                   = 79,
 102         SAI6_CLK_ROOT                   = 80,
 103         ENET_QOS_CLK_ROOT               = 81,
 104         ENET_QOS_TIMER_CLK_ROOT         = 82,
 105         ENET_REF_CLK_ROOT               = 83,
 106         ENET_TIMER_CLK_ROOT             = 84,
 107         ENET_PHY_REF_CLK_ROOT           = 85,
 108         NAND_CLK_ROOT                   = 86,
 109         QSPI_CLK_ROOT                   = 87,
 110         USDHC1_CLK_ROOT                 = 88,
 111         USDHC2_CLK_ROOT                 = 89,
 112         I2C1_CLK_ROOT                   = 90,
 113         I2C2_CLK_ROOT                   = 91,
 114         I2C3_CLK_ROOT                   = 92,
 115         I2C4_CLK_ROOT                   = 93,
 116         UART1_CLK_ROOT                  = 94,
 117         UART2_CLK_ROOT                  = 95,
 118         UART3_CLK_ROOT                  = 96,
 119         UART4_CLK_ROOT                  = 97,
 120         USB_CORE_REF_CLK_ROOT           = 98,
 121         USB_PHY_REF_CLK_ROOT            = 99,
 122         GIC_CLK_ROOT                    = 100,
 123         ECSPI1_CLK_ROOT                 = 101,
 124         ECSPI2_CLK_ROOT                 = 102,
 125         PWM1_CLK_ROOT                   = 103,
 126         PWM2_CLK_ROOT                   = 104,
 127         PWM3_CLK_ROOT                   = 105,
 128         PWM4_CLK_ROOT                   = 106,
 129         GPT1_CLK_ROOT                   = 107,
 130         GPT2_CLK_ROOT                   = 108,
 131         GPT3_CLK_ROOT                   = 109,
 132         GPT4_CLK_ROOT                   = 110,
 133         GPT5_CLK_ROOT                   = 111,
 134         GPT6_CLK_ROOT                   = 112,
 135         TRACE_CLK_ROOT                  = 113,
 136         WDOG_CLK_ROOT                   = 114,
 137         WRCLK_CLK_ROOT                  = 115,
 138         IPP_DO_CLKO1                    = 116,
 139         IPP_DO_CLKO2                    = 117,
 140         HDMI_FDCC_TST_CLK_ROOT          = 118,
 141         HDMI_27M_CLK_ROOT               = 119,
 142         HDMI_REF_266M_CLK_ROOT          = 120,
 143         USDHC3_CLK_ROOT                 = 121,
 144         MEDIA_CAM1_PIX_CLK_ROOT         = 122,
 145         MEDIA_MIPI_PHY1_REF_CLK_ROOT    = 123,
 146         MEDIA_DISP1_PIX_CLK_ROOT        = 124,
 147         MEDIA_CAM2_PIX_CLK_ROOT         = 125,
 148         MEDIA_LDB_CLK_ROOT      = 126,
 149         MEMREPAIR_CLK_ROOT      = 127,
 150         MEDIA_MIPI_TEST_BYTE_CLK        = 130,
 151         ECSPI3_CLK_ROOT                 = 131,
 152         PDM_CLK_ROOT                    = 132,
 153         VPU_VC8000E_CLK_ROOT            = 133,
 154         SAI7_CLK_ROOT                   = 134,
 155         CLK_ROOT_MAX,
 156 };
 157 #elif defined(CONFIG_IMX8MN)
 158 enum clk_root_index {
 159         ARM_A53_CLK_ROOT                = 0,
 160         ARM_M7_CLK_ROOT                 = 1,
 161         GPU_CORE_CLK_ROOT               = 3,
 162         GPU_SHADER_CLK_ROOT             = 4,
 163         MAIN_AXI_CLK_ROOT               = 16,
 164         ENET_AXI_CLK_ROOT               = 17,
 165         NAND_USDHC_BUS_CLK_ROOT         = 18,
 166         DISPLAY_AXI_CLK_ROOT            = 20,
 167         DISPLAY_APB_CLK_ROOT            = 21,
 168         USB_BUS_CLK_ROOT                = 23,
 169         GPU_AXI_CLK_ROOT                = 24,
 170         GPU_AHB_CLK_ROOT                = 25,
 171         NOC_CLK_ROOT                    = 26,
 172         AHB_CLK_ROOT                    = 32,
 173         IPG_CLK_ROOT                    = 33,
 174         AUDIO_AHB_CLK_ROOT              = 34,
 175         DRAM_SEL_CFG                    = 48,
 176         CORE_SEL_CFG                    = 49,
 177         DRAM_ALT_CLK_ROOT               = 64,
 178         DRAM_APB_CLK_ROOT               = 65,
 179         DISPLAY_PIXEL_CLK_ROOT          = 74,
 180         SAI2_CLK_ROOT                   = 76,
 181         SAI3_CLK_ROOT                   = 77,
 182         SAI5_CLK_ROOT                   = 79,
 183         SAI6_CLK_ROOT                   = 80,
 184         SPDIF1_CLK_ROOT                 = 81,
 185         ENET_REF_CLK_ROOT               = 83,
 186         ENET_TIMER_CLK_ROOT             = 84,
 187         ENET_PHY_REF_CLK_ROOT           = 85,
 188         NAND_CLK_ROOT                   = 86,
 189         QSPI_CLK_ROOT                   = 87,
 190         USDHC1_CLK_ROOT                 = 88,
 191         USDHC2_CLK_ROOT                 = 89,
 192         I2C1_CLK_ROOT                   = 90,
 193         I2C2_CLK_ROOT                   = 91,
 194         I2C3_CLK_ROOT                   = 92,
 195         I2C4_CLK_ROOT                   = 93,
 196         UART1_CLK_ROOT                  = 94,
 197         UART2_CLK_ROOT                  = 95,
 198         UART3_CLK_ROOT                  = 96,
 199         UART4_CLK_ROOT                  = 97,
 200         USB_CORE_REF_CLK_ROOT           = 98,
 201         USB_PHY_REF_CLK_ROOT            = 99,
 202         GIC_CLK_ROOT                    = 100,
 203         ECSPI1_CLK_ROOT                 = 101,
 204         ECSPI2_CLK_ROOT                 = 102,
 205         PWM1_CLK_ROOT                   = 103,
 206         PWM2_CLK_ROOT                   = 104,
 207         PWM3_CLK_ROOT                   = 105,
 208         PWM4_CLK_ROOT                   = 106,
 209         GPT1_CLK_ROOT                   = 107,
 210         GPT2_CLK_ROOT                   = 108,
 211         GPT3_CLK_ROOT                   = 109,
 212         GPT4_CLK_ROOT                   = 110,
 213         GPT5_CLK_ROOT                   = 111,
 214         GPT6_CLK_ROOT                   = 112,
 215         TRACE_CLK_ROOT                  = 113,
 216         WDOG_CLK_ROOT                   = 114,
 217         WRCLK_CLK_ROOT                  = 115,
 218         IPP_DO_CLKO1                    = 116,
 219         IPP_DO_CLKO2                    = 117,
 220         MIPI_DSI_CORE_CLK_ROOT          = 118,
 221         DISPLAY_DSI_PHY_REF_CLK_ROOT    = 119,
 222         MIPI_DSI_DBI_CLK_ROOT           = 120,
 223         USDHC3_CLK_ROOT                 = 121,
 224         DISPLAY_CAMERA_PIXEL_CLK_ROOT   = 122,
 225         MIPI_CSI1_PHY_REF_CLK_ROOT      = 123,
 226         MIPI_CSI2_PHY_REF_CLK_ROOT      = 126,
 227         MIPI_CSI2_ESC_CLK_ROOT          = 127,
 228         ECSPI3_CLK_ROOT                 = 131,
 229         PDM_CLK_ROOT                    = 132,
 230         SAI7_CLK_ROOT                   = 134,
 231         CLK_ROOT_MAX,
 232 };
 233 #else
 234 enum clk_root_index {
 235         ARM_A53_CLK_ROOT                = 0,
 236         ARM_M4_CLK_ROOT                 = 1,
 237         VPU_A53_CLK_ROOT                = 2,
 238         GPU3D_CLK_ROOT                  = 3,
 239         GPU2D_CLK_ROOT                  = 4,
 240         MAIN_AXI_CLK_ROOT               = 16,
 241         ENET_AXI_CLK_ROOT               = 17,
 242         NAND_USDHC_BUS_CLK_ROOT         = 18,
 243         VPU_BUS_CLK_ROOT                = 19,
 244         DISPLAY_AXI_CLK_ROOT            = 20,
 245         DISPLAY_APB_CLK_ROOT            = 21,
 246         DISPLAY_RTRM_CLK_ROOT           = 22,
 247         USB_BUS_CLK_ROOT                = 23,
 248         GPU_AXI_CLK_ROOT                = 24,
 249         GPU_AHB_CLK_ROOT                = 25,
 250         NOC_CLK_ROOT                    = 26,
 251         NOC_APB_CLK_ROOT                = 27,
 252         AHB_CLK_ROOT                    = 32,
 253         IPG_CLK_ROOT                    = 33,
 254         AUDIO_AHB_CLK_ROOT              = 34,
 255         MIPI_DSI_ESC_RX_CLK_ROOT        = 36,
 256         DRAM_SEL_CFG                    = 48,
 257         CORE_SEL_CFG                    = 49,
 258         DRAM_ALT_CLK_ROOT               = 64,
 259         DRAM_APB_CLK_ROOT               = 65,
 260         VPU_G1_CLK_ROOT                 = 66,
 261         VPU_G2_CLK_ROOT                 = 67,
 262         DISPLAY_DTRC_CLK_ROOT           = 68,
 263         DISPLAY_DC8000_CLK_ROOT         = 69,
 264         PCIE_CTRL_CLK_ROOT              = 70,
 265         PCIE_PHY_CLK_ROOT               = 71,
 266         PCIE_AUX_CLK_ROOT               = 72,
 267         DC_PIXEL_CLK_ROOT               = 73,
 268         LCDIF_PIXEL_CLK_ROOT            = 74,
 269         SAI1_CLK_ROOT                   = 75,
 270         SAI2_CLK_ROOT                   = 76,
 271         SAI3_CLK_ROOT                   = 77,
 272         SAI4_CLK_ROOT                   = 78,
 273         SAI5_CLK_ROOT                   = 79,
 274         SAI6_CLK_ROOT                   = 80,
 275         SPDIF1_CLK_ROOT                 = 81,
 276         SPDIF2_CLK_ROOT                 = 82,
 277         ENET_REF_CLK_ROOT               = 83,
 278         ENET_TIMER_CLK_ROOT             = 84,
 279         ENET_PHY_REF_CLK_ROOT           = 85,
 280         NAND_CLK_ROOT                   = 86,
 281         QSPI_CLK_ROOT                   = 87,
 282         USDHC1_CLK_ROOT                 = 88,
 283         USDHC2_CLK_ROOT                 = 89,
 284         I2C1_CLK_ROOT                   = 90,
 285         I2C2_CLK_ROOT                   = 91,
 286         I2C3_CLK_ROOT                   = 92,
 287         I2C4_CLK_ROOT                   = 93,
 288         UART1_CLK_ROOT                  = 94,
 289         UART2_CLK_ROOT                  = 95,
 290         UART3_CLK_ROOT                  = 96,
 291         UART4_CLK_ROOT                  = 97,
 292         USB_CORE_REF_CLK_ROOT           = 98,
 293         USB_PHY_REF_CLK_ROOT            = 99,
 294         GIC_CLK_ROOT                    = 100,
 295         ECSPI1_CLK_ROOT                 = 101,
 296         ECSPI2_CLK_ROOT                 = 102,
 297         PWM1_CLK_ROOT                   = 103,
 298         PWM2_CLK_ROOT                   = 104,
 299         PWM3_CLK_ROOT                   = 105,
 300         PWM4_CLK_ROOT                   = 106,
 301         GPT1_CLK_ROOT                   = 107,
 302         GPT2_CLK_ROOT                   = 108,
 303         GPT3_CLK_ROOT                   = 109,
 304         GPT4_CLK_ROOT                   = 110,
 305         GPT5_CLK_ROOT                   = 111,
 306         GPT6_CLK_ROOT                   = 112,
 307         TRACE_CLK_ROOT                  = 113,
 308         WDOG_CLK_ROOT                   = 114,
 309         WRCLK_CLK_ROOT                  = 115,
 310         IPP_DO_CLKO1                    = 116,
 311         IPP_DO_CLKO2                    = 117,
 312         MIPI_DSI_CORE_CLK_ROOT          = 118,
 313         MIPI_DSI_PHY_REF_CLK_ROOT       = 119,
 314         MIPI_DSI_DBI_CLK_ROOT           = 120,
 315         USDHC3_CLK_ROOT                 = 121,
 316         MIPI_CSI1_CORE_CLK_ROOT         = 122,
 317         MIPI_CSI1_PHY_REF_CLK_ROOT      = 123,
 318         MIPI_CSI1_ESC_CLK_ROOT          = 124,
 319         MIPI_CSI2_CORE_CLK_ROOT         = 125,
 320         MIPI_CSI2_PHY_REF_CLK_ROOT      = 126,
 321         MIPI_CSI2_ESC_CLK_ROOT          = 127,
 322         PCIE2_CTRL_CLK_ROOT             = 128,
 323         PCIE2_PHY_CLK_ROOT              = 129,
 324         PCIE2_AUX_CLK_ROOT              = 130,
 325         ECSPI3_CLK_ROOT                 = 131,
 326         PDM_CLK_ROOT                    = 132,
 327         VPU_H1_CLK_ROOT                 = 133,
 328         CLK_ROOT_MAX,
 329 };
 330 #endif
 331
 332 enum clk_root_src {
 333         OSC_24M_CLK,
 334         ARM_PLL_CLK,
 335         DRAM_PLL1_CLK,
 336         VIDEO_PLL2_CLK,
 337         VPU_PLL_CLK,
 338         GPU_PLL_CLK,
 339         SYSTEM_PLL1_800M_CLK,
 340         SYSTEM_PLL1_400M_CLK,
 341         SYSTEM_PLL1_266M_CLK,
 342         SYSTEM_PLL1_200M_CLK,
 343         SYSTEM_PLL1_160M_CLK,
 344         SYSTEM_PLL1_133M_CLK,
 345         SYSTEM_PLL1_100M_CLK,
 346         SYSTEM_PLL1_80M_CLK,
 347         SYSTEM_PLL1_40M_CLK,
 348         SYSTEM_PLL2_1000M_CLK,
 349         SYSTEM_PLL2_500M_CLK,
 350         SYSTEM_PLL2_333M_CLK,
 351         SYSTEM_PLL2_250M_CLK,
 352         SYSTEM_PLL2_200M_CLK,
 353         SYSTEM_PLL2_166M_CLK,
 354         SYSTEM_PLL2_125M_CLK,
 355         SYSTEM_PLL2_100M_CLK,
 356         SYSTEM_PLL2_50M_CLK,
 357         SYSTEM_PLL3_CLK,
 358         AUDIO_PLL1_CLK,
 359         AUDIO_PLL2_CLK,
 360         VIDEO_PLL_CLK,
 361         OSC_32K_CLK,
 362         EXT_CLK_1,
 363         EXT_CLK_2,
 364         EXT_CLK_3,
 365         EXT_CLK_4,
 366         OSC_HDMI_CLK,
 367         ARM_A53_ALT_CLK,
 368 };
 369
 370 enum clk_ccgr_index {
 371         CCGR_DVFS = 0,
 372         CCGR_ANAMIX = 1,
 373         CCGR_CPU = 2,
 374         CCGR_CSU = 3,
 375         CCGR_DEBUG = 4,
 376         CCGR_DDR1 = 5,
 377         CCGR_ECSPI1 = 7,
 378         CCGR_ECSPI2 = 8,
 379         CCGR_ECSPI3 = 9,
 380         CCGR_ENET1 = 10,
 381         CCGR_GPIO1 = 11,
 382         CCGR_GPIO2 = 12,
 383         CCGR_GPIO3 = 13,
 384         CCGR_GPIO4 = 14,
 385         CCGR_GPIO5 = 15,
 386         CCGR_GPT1 = 16,
 387         CCGR_GPT2 = 17,
 388         CCGR_GPT3 = 18,
 389         CCGR_GPT4 = 19,
 390         CCGR_AAM_8MP = 20,
 391         CCGR_GPT5 = 20,
 392         CCGR_GPT6 = 21,
 393         CCGR_HS = 22,
 394         CCGR_I2C1 = 23,
 395         CCGR_I2C2 = 24,
 396         CCGR_I2C3 = 25,
 397         CCGR_I2C4 = 26,
 398         CCGR_IOMUX = 27,
 399         CCGR_IOMUX1 = 28,
 400         CCGR_IOMUX2 = 29,
 401         CCGR_IOMUX3 = 30,
 402         CCGR_IOMUX4 = 31,
 403         CCGR_SNVSMIX_IPG_CLK = 32,
 404         CCGR_MU = 33,
 405         CCGR_OCOTP = 34,
 406         CCGR_OCRAM = 35,
 407         CCGR_OCRAM_S = 36,
 408         CCGR_PCIE = 37,
 409         CCGR_PERFMON1 = 38,
 410         CCGR_PERFMON2 = 39,
 411         CCGR_PWM1 = 40,
 412         CCGR_PWM2 = 41,
 413         CCGR_PWM3 = 42,
 414         CCGR_PWM4 = 43,
 415         CCGR_QOS = 44,
 416         CCGR_QOS_DISPMIX = 45,
 417         CCGR_QOS_ETHENET = 46,
 418         CCGR_QSPI = 47,
 419         CCGR_RAWNAND = 48,
 420         CCGR_RDC = 49,
 421         CCGR_ROM = 50,
 422         CCGR_I2C5_8MP = 51,
 423         CCGR_SAI1 = 51,
 424         CCGR_I2C6_8MP = 52,
 425         CCGR_SAI2 = 52,
 426         CCGR_SAI3 = 53,
 427         CCGR_SAI4 = 54,
 428         CCGR_SAI5 = 55,
 429         CCGR_SAI6 = 56,
 430         CCGR_SCTR = 57,
 431         CCGR_SDMA1 = 58,
 432         CCGR_SDMA2 = 59,
 433         CCGR_SEC_DEBUG = 60,
 434         CCGR_SEMA1 = 61,
 435         CCGR_SEMA2 = 62,
 436         CCGR_IRQ_STEER_8MP = 63,
 437         CCGR_SIM_DISPLAY = 63,
 438         CCGR_SIM_ENET = 64,
 439         CCGR_SIM_M = 65,
 440         CCGR_SIM_MAIN = 66,
 441         CCGR_SIM_S = 67,
 442         CCGR_SIM_WAKEUP = 68,
 443         CCGR_GPU2D_8MP = 69,
 444         CCGR_SIM_HSIO = 69,
 445         CCGR_GPU3D_8MP = 70,
 446         CCGR_SIM_VPU = 70,
 447         CCGR_SNVS = 71,
 448         CCGR_TRACE = 72,
 449         CCGR_UART1 = 73,
 450         CCGR_UART2 = 74,
 451         CCGR_UART3 = 75,
 452         CCGR_UART4 = 76,
 453         CCGR_USB_MSCALE_PL301 = 77,
 454         CCGR_USB_PHY_8MP = 79,
 455         CCGR_GPU3D = 79,
 456         CCGR_USDHC1 = 81,
 457         CCGR_USDHC2 = 82,
 458         CCGR_WDOG1 = 83,
 459         CCGR_WDOG2 = 84,
 460         CCGR_WDOG3 = 85,
 461         CCGR_VPUG1 = 86,
 462         CCGR_GPU_BUS = 87,
 463         CCGR_VPUH1 = 89,
 464         CCGR_VPUG2 = 90,
 465         CCGR_PDM = 91,
 466         CCGR_GIC = 92,
 467         CCGR_DISPMIX = 93,
 468         CCGR_USDHC3 = 94,
 469         CCGR_SDMA3 = 95,
 470         CCGR_XTAL = 96,
 471         CCGR_PLL = 97,
 472         CCGR_TEMP_SENSOR = 98,
 473         CCGR_VPUMIX_BUS = 99,
 474         CCGR_SAI7 = 101,
 475         CCGR_GPU2D = 102,
 476         CCGR_MAX
 477 };
 478
 479 enum clk_src_index {
 480         CLK_SRC_CKIL_SYNC_REQ = 0,
 481         CLK_SRC_ARM_PLL_EN = 1,
 482         CLK_SRC_GPU_PLL_EN = 2,
 483         CLK_SRC_VPU_PLL_EN = 3,
 484         CLK_SRC_DRAM_PLL_EN = 4,
 485         CLK_SRC_SYSTEM_PLL1_EN = 5,
 486         CLK_SRC_SYSTEM_PLL2_EN = 6,
 487         CLK_SRC_SYSTEM_PLL3_EN = 7,
 488         CLK_SRC_AUDIO_PLL1_EN = 8,
 489         CLK_SRC_AUDIO_PLL2_EN = 9,
 490         CLK_SRC_VIDEO_PLL1_EN = 10,
 491         CLK_SRC_RESERVED = 11,
 492         CLK_SRC_ARM_PLL = 12,
 493         CLK_SRC_GPU_PLL = 13,
 494         CLK_SRC_VPU_PLL = 14,
 495         CLK_SRC_DRAM_PLL = 15,
 496         CLK_SRC_SYSTEM_PLL1_800M = 16,
 497         CLK_SRC_SYSTEM_PLL1_400M = 17,
 498         CLK_SRC_SYSTEM_PLL1_266M = 18,
 499         CLK_SRC_SYSTEM_PLL1_200M = 19,
 500         CLK_SRC_SYSTEM_PLL1_160M = 20,
 501         CLK_SRC_SYSTEM_PLL1_133M = 21,
 502         CLK_SRC_SYSTEM_PLL1_100M = 22,
 503         CLK_SRC_SYSTEM_PLL1_80M = 23,
 504         CLK_SRC_SYSTEM_PLL1_40M = 24,
 505         CLK_SRC_SYSTEM_PLL2_1000M = 25,
 506         CLK_SRC_SYSTEM_PLL2_500M = 26,
 507         CLK_SRC_SYSTEM_PLL2_333M = 27,
 508         CLK_SRC_SYSTEM_PLL2_250M = 28,
 509         CLK_SRC_SYSTEM_PLL2_200M = 29,
 510         CLK_SRC_SYSTEM_PLL2_166M = 30,
 511         CLK_SRC_SYSTEM_PLL2_125M = 31,
 512         CLK_SRC_SYSTEM_PLL2_100M = 32,
 513         CLK_SRC_SYSTEM_PLL2_50M = 33,
 514         CLK_SRC_SYSTEM_PLL3 = 34,
 515         CLK_SRC_AUDIO_PLL1 = 35,
 516         CLK_SRC_AUDIO_PLL2 = 36,
 517         CLK_SRC_VIDEO_PLL1 = 37,
 518 };
 519
 520 #define INTPLL_LOCK_MASK                        BIT(31)
 521 #define INTPLL_LOCK_SEL_MASK                    BIT(29)
 522 #define INTPLL_EXT_BYPASS_MASK                  BIT(28)
 523 #define INTPLL_DIV20_CLKE_MASK                  BIT(27)
 524 #define INTPLL_DIV20_CLKE_OVERRIDE_MASK         BIT(26)
 525 #define INTPLL_DIV10_CLKE_MASK                  BIT(25)
 526 #define INTPLL_DIV10_CLKE_OVERRIDE_MASK         BIT(24)
 527 #define INTPLL_DIV8_CLKE_MASK                   BIT(23)
 528 #define INTPLL_DIV8_CLKE_OVERRIDE_MASK          BIT(22)
 529 #define INTPLL_DIV6_CLKE_MASK                   BIT(21)
 530 #define INTPLL_DIV6_CLKE_OVERRIDE_MASK          BIT(20)
 531 #define INTPLL_DIV5_CLKE_MASK                   BIT(19)
 532 #define INTPLL_DIV5_CLKE_OVERRIDE_MASK          BIT(18)
 533 #define INTPLL_DIV4_CLKE_MASK                   BIT(17)
 534 #define INTPLL_DIV4_CLKE_OVERRIDE_MASK          BIT(16)
 535 #define INTPLL_DIV3_CLKE_MASK                   BIT(15)
 536 #define INTPLL_DIV3_CLKE_OVERRIDE_MASK          BIT(14)
 537 #define INTPLL_DIV2_CLKE_MASK                   BIT(13)
 538 #define INTPLL_DIV2_CLKE_OVERRIDE_MASK          BIT(12)
 539 #define INTPLL_CLKE_MASK                        BIT(11)
 540 #define INTPLL_CLKE_OVERRIDE_MASK               BIT(10)
 541 #define INTPLL_RST_MASK                         BIT(9)
 542 #define INTPLL_RST_OVERRIDE_MASK                BIT(8)
 543 #define INTPLL_BYPASS_MASK                      BIT(4)
 544 #define INTPLL_PAD_CLK_SEL_MASK                 GENMASK(3, 2)
 545 #define INTPLL_REF_CLK_SEL_MASK                 GENMASK(1, 0)
 546
 547 #define INTPLL_MAIN_DIV_MASK            GENMASK(21, 12)
 548 #define INTPLL_MAIN_DIV_VAL(n)          ((n << 12) & GENMASK(21, 12))
 549 #define INTPLL_MAIN_DIV_SHIFT           12
 550 #define INTPLL_PRE_DIV_MASK             GENMASK(9, 4)
 551 #define INTPLL_PRE_DIV_VAL(n)           ((n << 4) & GENMASK(9, 4))
 552 #define INTPLL_PRE_DIV_SHIFT            4
 553 #define INTPLL_POST_DIV_MASK            GENMASK(2, 0)
 554 #define INTPLL_POST_DIV_VAL(n)          ((n << 0) & GENMASK(2, 0))
 555 #define INTPLL_POST_DIV_SHIFT           0
 556
 557 #define INTPLL_LOCK_CON_DLY_MASK        GENMASK(5, 4)
 558 #define INTPLL_LOCK_CON_DLY_SHIFT       4
 559 #define INTPLL_LOCK_CON_OUT_MASK        GENMASK(3, 2)
 560 #define INTPLL_LOCK_CON_OUT_SHIFT       2
 561 #define INTPLL_LOCK_CON_IN_MASK         GENMASK(1, 0)
 562 #define INTPLL_LOCK_CON_IN_SHIFT        0
 563
 564 #define INTPLL_LRD_EN_MASK              BIT(21)
 565 #define INTPLL_FOUT_MASK                BIT(20)
 566 #define INTPLL_AFC_SEL_MASK             BIT(19)
 567 #define INTPLL_PBIAS_CTRL_MASK          BIT(18)
 568 #define INTPLL_PBIAS_CTRL_EN_MASK       BIT(17)
 569 #define INTPLL_AFCINIT_SEL_MASK         BIT(16)
 570 #define INTPLL_FSEL_MASK                BIT(14)
 571 #define INTPLL_FEED_EN_MASK             BIT(13)
 572 #define INTPLL_EXTAFC_MASK              GENMASK(7, 3)
 573 #define INTPLL_AFC_EN_MASK              BIT(2)
 574 #define INTPLL_ICP_MASK                 GENMASK(1, 0)
 575
 576 #endif