1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2018-2019 NXP
5 * Peng Fan <peng.fan@nxp.com>
8 #ifndef _ASM_ARCH_IMX8MM_CLOCK_H
9 #define _ASM_ARCH_IMX8MM_CLOCK_H
11 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
20 #define LOCK_STATUS BIT(31)
21 #define LOCK_SEL_MASK BIT(29)
22 #define CLKE_MASK BIT(11)
23 #define RST_MASK BIT(9)
24 #define BYPASS_MASK BIT(4)
26 #define MDIV_MASK GENMASK(21, 12)
28 #define PDIV_MASK GENMASK(9, 4)
30 #define SDIV_MASK GENMASK(2, 0)
32 #define KDIV_MASK GENMASK(15, 0)
34 struct imx_int_pll_rate_table {
60 GPU3D_CORE_CLK_ROOT = 3,
61 GPU3D_SHADER_CLK_ROOT = 4,
63 AUDIO_AXI_CLK_ROOT = 6,
64 HSIO_AXI_CLK_ROOT = 7,
65 MEDIA_ISP_CLK_ROOT = 8,
66 MAIN_AXI_CLK_ROOT = 16,
67 ENET_AXI_CLK_ROOT = 17,
68 NAND_USDHC_BUS_CLK_ROOT = 18,
69 VPU_BUS_CLK_ROOT = 19,
70 MEDIA_AXI_CLK_ROOT = 20,
71 MEDIA_APB_CLK_ROOT = 21,
72 HDMI_APB_CLK_ROOT = 22,
73 HDMI_AXI_CLK_ROOT = 23,
74 GPU_AXI_CLK_ROOT = 24,
75 GPU_AHB_CLK_ROOT = 25,
82 AUDIO_AHB_CLK_ROOT = 34,
83 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
84 MEDIA_DISP2_CLK_ROOT = 38,
87 DRAM_ALT_CLK_ROOT = 64,
88 DRAM_APB_CLK_ROOT = 65,
93 PCIE_PHY_CLK_ROOT = 71,
94 PCIE_AUX_CLK_ROOT = 72,
103 ENET_QOS_CLK_ROOT = 81,
104 ENET_QOS_TIMER_CLK_ROOT = 82,
105 ENET_REF_CLK_ROOT = 83,
106 ENET_TIMER_CLK_ROOT = 84,
107 ENET_PHY_REF_CLK_ROOT = 85,
110 USDHC1_CLK_ROOT = 88,
111 USDHC2_CLK_ROOT = 89,
120 USB_CORE_REF_CLK_ROOT = 98,
121 USB_PHY_REF_CLK_ROOT = 99,
123 ECSPI1_CLK_ROOT = 101,
124 ECSPI2_CLK_ROOT = 102,
135 TRACE_CLK_ROOT = 113,
137 WRCLK_CLK_ROOT = 115,
140 HDMI_FDCC_TST_CLK_ROOT = 118,
141 HDMI_27M_CLK_ROOT = 119,
142 HDMI_REF_266M_CLK_ROOT = 120,
143 USDHC3_CLK_ROOT = 121,
144 MEDIA_CAM1_PIX_CLK_ROOT = 122,
145 MEDIA_MIPI_PHY1_REF_CLK_ROOT = 123,
146 MEDIA_DISP1_PIX_CLK_ROOT = 124,
147 MEDIA_CAM2_PIX_CLK_ROOT = 125,
148 MEDIA_LDB_CLK_ROOT = 126,
149 MEMREPAIR_CLK_ROOT = 127,
150 MEDIA_MIPI_TEST_BYTE_CLK = 130,
151 ECSPI3_CLK_ROOT = 131,
153 VPU_VC8000E_CLK_ROOT = 133,
157 #elif defined(CONFIG_IMX8MN)
158 enum clk_root_index {
159 ARM_A53_CLK_ROOT = 0,
161 GPU_CORE_CLK_ROOT = 3,
162 GPU_SHADER_CLK_ROOT = 4,
163 MAIN_AXI_CLK_ROOT = 16,
164 ENET_AXI_CLK_ROOT = 17,
165 NAND_USDHC_BUS_CLK_ROOT = 18,
166 DISPLAY_AXI_CLK_ROOT = 20,
167 DISPLAY_APB_CLK_ROOT = 21,
168 USB_BUS_CLK_ROOT = 23,
169 GPU_AXI_CLK_ROOT = 24,
170 GPU_AHB_CLK_ROOT = 25,
174 AUDIO_AHB_CLK_ROOT = 34,
177 DRAM_ALT_CLK_ROOT = 64,
178 DRAM_APB_CLK_ROOT = 65,
179 DISPLAY_PIXEL_CLK_ROOT = 74,
184 SPDIF1_CLK_ROOT = 81,
185 ENET_REF_CLK_ROOT = 83,
186 ENET_TIMER_CLK_ROOT = 84,
187 ENET_PHY_REF_CLK_ROOT = 85,
190 USDHC1_CLK_ROOT = 88,
191 USDHC2_CLK_ROOT = 89,
200 USB_CORE_REF_CLK_ROOT = 98,
201 USB_PHY_REF_CLK_ROOT = 99,
203 ECSPI1_CLK_ROOT = 101,
204 ECSPI2_CLK_ROOT = 102,
215 TRACE_CLK_ROOT = 113,
217 WRCLK_CLK_ROOT = 115,
220 MIPI_DSI_CORE_CLK_ROOT = 118,
221 DISPLAY_DSI_PHY_REF_CLK_ROOT = 119,
222 MIPI_DSI_DBI_CLK_ROOT = 120,
223 USDHC3_CLK_ROOT = 121,
224 DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122,
225 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
226 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
227 MIPI_CSI2_ESC_CLK_ROOT = 127,
228 ECSPI3_CLK_ROOT = 131,
234 enum clk_root_index {
235 ARM_A53_CLK_ROOT = 0,
237 VPU_A53_CLK_ROOT = 2,
240 MAIN_AXI_CLK_ROOT = 16,
241 ENET_AXI_CLK_ROOT = 17,
242 NAND_USDHC_BUS_CLK_ROOT = 18,
243 VPU_BUS_CLK_ROOT = 19,
244 DISPLAY_AXI_CLK_ROOT = 20,
245 DISPLAY_APB_CLK_ROOT = 21,
246 DISPLAY_RTRM_CLK_ROOT = 22,
247 USB_BUS_CLK_ROOT = 23,
248 GPU_AXI_CLK_ROOT = 24,
249 GPU_AHB_CLK_ROOT = 25,
251 NOC_APB_CLK_ROOT = 27,
254 AUDIO_AHB_CLK_ROOT = 34,
255 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
258 DRAM_ALT_CLK_ROOT = 64,
259 DRAM_APB_CLK_ROOT = 65,
260 VPU_G1_CLK_ROOT = 66,
261 VPU_G2_CLK_ROOT = 67,
262 DISPLAY_DTRC_CLK_ROOT = 68,
263 DISPLAY_DC8000_CLK_ROOT = 69,
264 PCIE_CTRL_CLK_ROOT = 70,
265 PCIE_PHY_CLK_ROOT = 71,
266 PCIE_AUX_CLK_ROOT = 72,
267 DC_PIXEL_CLK_ROOT = 73,
268 LCDIF_PIXEL_CLK_ROOT = 74,
275 SPDIF1_CLK_ROOT = 81,
276 SPDIF2_CLK_ROOT = 82,
277 ENET_REF_CLK_ROOT = 83,
278 ENET_TIMER_CLK_ROOT = 84,
279 ENET_PHY_REF_CLK_ROOT = 85,
282 USDHC1_CLK_ROOT = 88,
283 USDHC2_CLK_ROOT = 89,
292 USB_CORE_REF_CLK_ROOT = 98,
293 USB_PHY_REF_CLK_ROOT = 99,
295 ECSPI1_CLK_ROOT = 101,
296 ECSPI2_CLK_ROOT = 102,
307 TRACE_CLK_ROOT = 113,
309 WRCLK_CLK_ROOT = 115,
312 MIPI_DSI_CORE_CLK_ROOT = 118,
313 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
314 MIPI_DSI_DBI_CLK_ROOT = 120,
315 USDHC3_CLK_ROOT = 121,
316 MIPI_CSI1_CORE_CLK_ROOT = 122,
317 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
318 MIPI_CSI1_ESC_CLK_ROOT = 124,
319 MIPI_CSI2_CORE_CLK_ROOT = 125,
320 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
321 MIPI_CSI2_ESC_CLK_ROOT = 127,
322 PCIE2_CTRL_CLK_ROOT = 128,
323 PCIE2_PHY_CLK_ROOT = 129,
324 PCIE2_AUX_CLK_ROOT = 130,
325 ECSPI3_CLK_ROOT = 131,
327 VPU_H1_CLK_ROOT = 133,
339 SYSTEM_PLL1_800M_CLK,
340 SYSTEM_PLL1_400M_CLK,
341 SYSTEM_PLL1_266M_CLK,
342 SYSTEM_PLL1_200M_CLK,
343 SYSTEM_PLL1_160M_CLK,
344 SYSTEM_PLL1_133M_CLK,
345 SYSTEM_PLL1_100M_CLK,
348 SYSTEM_PLL2_1000M_CLK,
349 SYSTEM_PLL2_500M_CLK,
350 SYSTEM_PLL2_333M_CLK,
351 SYSTEM_PLL2_250M_CLK,
352 SYSTEM_PLL2_200M_CLK,
353 SYSTEM_PLL2_166M_CLK,
354 SYSTEM_PLL2_125M_CLK,
355 SYSTEM_PLL2_100M_CLK,
370 enum clk_ccgr_index {
403 CCGR_SNVSMIX_IPG_CLK = 32,
416 CCGR_QOS_DISPMIX = 45,
417 CCGR_QOS_ETHENET = 46,
436 CCGR_IRQ_STEER_8MP = 63,
437 CCGR_SIM_DISPLAY = 63,
442 CCGR_SIM_WAKEUP = 68,
453 CCGR_USB_MSCALE_PL301 = 77,
454 CCGR_USB_PHY_8MP = 79,
472 CCGR_TEMP_SENSOR = 98,
473 CCGR_VPUMIX_BUS = 99,
480 CLK_SRC_CKIL_SYNC_REQ = 0,
481 CLK_SRC_ARM_PLL_EN = 1,
482 CLK_SRC_GPU_PLL_EN = 2,
483 CLK_SRC_VPU_PLL_EN = 3,
484 CLK_SRC_DRAM_PLL_EN = 4,
485 CLK_SRC_SYSTEM_PLL1_EN = 5,
486 CLK_SRC_SYSTEM_PLL2_EN = 6,
487 CLK_SRC_SYSTEM_PLL3_EN = 7,
488 CLK_SRC_AUDIO_PLL1_EN = 8,
489 CLK_SRC_AUDIO_PLL2_EN = 9,
490 CLK_SRC_VIDEO_PLL1_EN = 10,
491 CLK_SRC_RESERVED = 11,
492 CLK_SRC_ARM_PLL = 12,
493 CLK_SRC_GPU_PLL = 13,
494 CLK_SRC_VPU_PLL = 14,
495 CLK_SRC_DRAM_PLL = 15,
496 CLK_SRC_SYSTEM_PLL1_800M = 16,
497 CLK_SRC_SYSTEM_PLL1_400M = 17,
498 CLK_SRC_SYSTEM_PLL1_266M = 18,
499 CLK_SRC_SYSTEM_PLL1_200M = 19,
500 CLK_SRC_SYSTEM_PLL1_160M = 20,
501 CLK_SRC_SYSTEM_PLL1_133M = 21,
502 CLK_SRC_SYSTEM_PLL1_100M = 22,
503 CLK_SRC_SYSTEM_PLL1_80M = 23,
504 CLK_SRC_SYSTEM_PLL1_40M = 24,
505 CLK_SRC_SYSTEM_PLL2_1000M = 25,
506 CLK_SRC_SYSTEM_PLL2_500M = 26,
507 CLK_SRC_SYSTEM_PLL2_333M = 27,
508 CLK_SRC_SYSTEM_PLL2_250M = 28,
509 CLK_SRC_SYSTEM_PLL2_200M = 29,
510 CLK_SRC_SYSTEM_PLL2_166M = 30,
511 CLK_SRC_SYSTEM_PLL2_125M = 31,
512 CLK_SRC_SYSTEM_PLL2_100M = 32,
513 CLK_SRC_SYSTEM_PLL2_50M = 33,
514 CLK_SRC_SYSTEM_PLL3 = 34,
515 CLK_SRC_AUDIO_PLL1 = 35,
516 CLK_SRC_AUDIO_PLL2 = 36,
517 CLK_SRC_VIDEO_PLL1 = 37,
520 #define INTPLL_LOCK_MASK BIT(31)
521 #define INTPLL_LOCK_SEL_MASK BIT(29)
522 #define INTPLL_EXT_BYPASS_MASK BIT(28)
523 #define INTPLL_DIV20_CLKE_MASK BIT(27)
524 #define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
525 #define INTPLL_DIV10_CLKE_MASK BIT(25)
526 #define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
527 #define INTPLL_DIV8_CLKE_MASK BIT(23)
528 #define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
529 #define INTPLL_DIV6_CLKE_MASK BIT(21)
530 #define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
531 #define INTPLL_DIV5_CLKE_MASK BIT(19)
532 #define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
533 #define INTPLL_DIV4_CLKE_MASK BIT(17)
534 #define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
535 #define INTPLL_DIV3_CLKE_MASK BIT(15)
536 #define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
537 #define INTPLL_DIV2_CLKE_MASK BIT(13)
538 #define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
539 #define INTPLL_CLKE_MASK BIT(11)
540 #define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
541 #define INTPLL_RST_MASK BIT(9)
542 #define INTPLL_RST_OVERRIDE_MASK BIT(8)
543 #define INTPLL_BYPASS_MASK BIT(4)
544 #define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
545 #define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
547 #define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
548 #define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
549 #define INTPLL_MAIN_DIV_SHIFT 12
550 #define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
551 #define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
552 #define INTPLL_PRE_DIV_SHIFT 4
553 #define INTPLL_POST_DIV_MASK GENMASK(2, 0)
554 #define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
555 #define INTPLL_POST_DIV_SHIFT 0
557 #define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
558 #define INTPLL_LOCK_CON_DLY_SHIFT 4
559 #define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
560 #define INTPLL_LOCK_CON_OUT_SHIFT 2
561 #define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
562 #define INTPLL_LOCK_CON_IN_SHIFT 0
564 #define INTPLL_LRD_EN_MASK BIT(21)
565 #define INTPLL_FOUT_MASK BIT(20)
566 #define INTPLL_AFC_SEL_MASK BIT(19)
567 #define INTPLL_PBIAS_CTRL_MASK BIT(18)
568 #define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
569 #define INTPLL_AFCINIT_SEL_MASK BIT(16)
570 #define INTPLL_FSEL_MASK BIT(14)
571 #define INTPLL_FEED_EN_MASK BIT(13)
572 #define INTPLL_EXTAFC_MASK GENMASK(7, 3)
573 #define INTPLL_AFC_EN_MASK BIT(2)
574 #define INTPLL_ICP_MASK GENMASK(1, 0)