1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2018-2019 NXP
5 * Peng Fan <peng.fan@nxp.com>
8 #ifndef _ASM_ARCH_IMX8MM_CLOCK_H
9 #define _ASM_ARCH_IMX8MM_CLOCK_H
11 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
20 #define LOCK_STATUS BIT(31)
21 #define LOCK_SEL_MASK BIT(29)
22 #define CLKE_MASK BIT(11)
23 #define RST_MASK BIT(9)
24 #define BYPASS_MASK BIT(4)
26 #define MDIV_MASK GENMASK(21, 12)
28 #define PDIV_MASK GENMASK(9, 4)
30 #define SDIV_MASK GENMASK(2, 0)
32 #define KDIV_MASK GENMASK(15, 0)
34 struct imx_int_pll_rate_table {
61 MAIN_AXI_CLK_ROOT = 16,
62 ENET_AXI_CLK_ROOT = 17,
63 NAND_USDHC_BUS_CLK_ROOT = 18,
64 VPU_BUS_CLK_ROOT = 19,
65 DISPLAY_AXI_CLK_ROOT = 20,
66 DISPLAY_APB_CLK_ROOT = 21,
67 DISPLAY_RTRM_CLK_ROOT = 22,
68 USB_BUS_CLK_ROOT = 23,
69 GPU_AXI_CLK_ROOT = 24,
70 GPU_AHB_CLK_ROOT = 25,
72 NOC_APB_CLK_ROOT = 27,
75 AUDIO_AHB_CLK_ROOT = 34,
76 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
79 DRAM_ALT_CLK_ROOT = 64,
80 DRAM_APB_CLK_ROOT = 65,
83 DISPLAY_DTRC_CLK_ROOT = 68,
84 DISPLAY_DC8000_CLK_ROOT = 69,
85 PCIE_CTRL_CLK_ROOT = 70,
86 PCIE_PHY_CLK_ROOT = 71,
87 PCIE_AUX_CLK_ROOT = 72,
88 DC_PIXEL_CLK_ROOT = 73,
89 LCDIF_PIXEL_CLK_ROOT = 74,
98 ENET_REF_CLK_ROOT = 83,
99 ENET_TIMER_CLK_ROOT = 84,
100 ENET_PHY_REF_CLK_ROOT = 85,
103 USDHC1_CLK_ROOT = 88,
104 USDHC2_CLK_ROOT = 89,
113 USB_CORE_REF_CLK_ROOT = 98,
114 USB_PHY_REF_CLK_ROOT = 99,
116 ECSPI1_CLK_ROOT = 101,
117 ECSPI2_CLK_ROOT = 102,
128 TRACE_CLK_ROOT = 113,
130 WRCLK_CLK_ROOT = 115,
133 MIPI_DSI_CORE_CLK_ROOT = 118,
134 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
135 MIPI_DSI_DBI_CLK_ROOT = 120,
136 USDHC3_CLK_ROOT = 121,
137 MIPI_CSI1_CORE_CLK_ROOT = 122,
138 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
139 MIPI_CSI1_ESC_CLK_ROOT = 124,
140 MIPI_CSI2_CORE_CLK_ROOT = 125,
141 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
142 MIPI_CSI2_ESC_CLK_ROOT = 127,
143 PCIE2_CTRL_CLK_ROOT = 128,
144 PCIE2_PHY_CLK_ROOT = 129,
145 PCIE2_AUX_CLK_ROOT = 130,
146 ECSPI3_CLK_ROOT = 131,
148 VPU_H1_CLK_ROOT = 133,
159 SYSTEM_PLL1_800M_CLK,
160 SYSTEM_PLL1_400M_CLK,
161 SYSTEM_PLL1_266M_CLK,
162 SYSTEM_PLL1_200M_CLK,
163 SYSTEM_PLL1_160M_CLK,
164 SYSTEM_PLL1_133M_CLK,
165 SYSTEM_PLL1_100M_CLK,
168 SYSTEM_PLL2_1000M_CLK,
169 SYSTEM_PLL2_500M_CLK,
170 SYSTEM_PLL2_333M_CLK,
171 SYSTEM_PLL2_250M_CLK,
172 SYSTEM_PLL2_200M_CLK,
173 SYSTEM_PLL2_166M_CLK,
174 SYSTEM_PLL2_125M_CLK,
175 SYSTEM_PLL2_100M_CLK,
189 enum clk_ccgr_index {
221 CCGR_SNVSMIX_IPG_CLK = 32,
234 CCGR_QOS_DISPMIX = 45,
235 CCGR_QOS_ETHENET = 46,
252 CCGR_SIM_DISPLAY = 63,
257 CCGR_SIM_WAKEUP = 68,
266 CCGR_USB_MSCALE_PL301 = 77,
284 CCGR_TEMP_SENSOR = 98,
285 CCGR_VPUMIX_BUS = 99,
291 CLK_SRC_CKIL_SYNC_REQ = 0,
292 CLK_SRC_ARM_PLL_EN = 1,
293 CLK_SRC_GPU_PLL_EN = 2,
294 CLK_SRC_VPU_PLL_EN = 3,
295 CLK_SRC_DRAM_PLL_EN = 4,
296 CLK_SRC_SYSTEM_PLL1_EN = 5,
297 CLK_SRC_SYSTEM_PLL2_EN = 6,
298 CLK_SRC_SYSTEM_PLL3_EN = 7,
299 CLK_SRC_AUDIO_PLL1_EN = 8,
300 CLK_SRC_AUDIO_PLL2_EN = 9,
301 CLK_SRC_VIDEO_PLL1_EN = 10,
302 CLK_SRC_RESERVED = 11,
303 CLK_SRC_ARM_PLL = 12,
304 CLK_SRC_GPU_PLL = 13,
305 CLK_SRC_VPU_PLL = 14,
306 CLK_SRC_DRAM_PLL = 15,
307 CLK_SRC_SYSTEM_PLL1_800M = 16,
308 CLK_SRC_SYSTEM_PLL1_400M = 17,
309 CLK_SRC_SYSTEM_PLL1_266M = 18,
310 CLK_SRC_SYSTEM_PLL1_200M = 19,
311 CLK_SRC_SYSTEM_PLL1_160M = 20,
312 CLK_SRC_SYSTEM_PLL1_133M = 21,
313 CLK_SRC_SYSTEM_PLL1_100M = 22,
314 CLK_SRC_SYSTEM_PLL1_80M = 23,
315 CLK_SRC_SYSTEM_PLL1_40M = 24,
316 CLK_SRC_SYSTEM_PLL2_1000M = 25,
317 CLK_SRC_SYSTEM_PLL2_500M = 26,
318 CLK_SRC_SYSTEM_PLL2_333M = 27,
319 CLK_SRC_SYSTEM_PLL2_250M = 28,
320 CLK_SRC_SYSTEM_PLL2_200M = 29,
321 CLK_SRC_SYSTEM_PLL2_166M = 30,
322 CLK_SRC_SYSTEM_PLL2_125M = 31,
323 CLK_SRC_SYSTEM_PLL2_100M = 32,
324 CLK_SRC_SYSTEM_PLL2_50M = 33,
325 CLK_SRC_SYSTEM_PLL3 = 34,
326 CLK_SRC_AUDIO_PLL1 = 35,
327 CLK_SRC_AUDIO_PLL2 = 36,
328 CLK_SRC_VIDEO_PLL1 = 37,
331 #define INTPLL_LOCK_MASK BIT(31)
332 #define INTPLL_LOCK_SEL_MASK BIT(29)
333 #define INTPLL_EXT_BYPASS_MASK BIT(28)
334 #define INTPLL_DIV20_CLKE_MASK BIT(27)
335 #define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
336 #define INTPLL_DIV10_CLKE_MASK BIT(25)
337 #define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
338 #define INTPLL_DIV8_CLKE_MASK BIT(23)
339 #define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
340 #define INTPLL_DIV6_CLKE_MASK BIT(21)
341 #define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
342 #define INTPLL_DIV5_CLKE_MASK BIT(19)
343 #define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
344 #define INTPLL_DIV4_CLKE_MASK BIT(17)
345 #define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
346 #define INTPLL_DIV3_CLKE_MASK BIT(15)
347 #define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
348 #define INTPLL_DIV2_CLKE_MASK BIT(13)
349 #define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
350 #define INTPLL_CLKE_MASK BIT(11)
351 #define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
352 #define INTPLL_RST_MASK BIT(9)
353 #define INTPLL_RST_OVERRIDE_MASK BIT(8)
354 #define INTPLL_BYPASS_MASK BIT(4)
355 #define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
356 #define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
358 #define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
359 #define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
360 #define INTPLL_MAIN_DIV_SHIFT 12
361 #define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
362 #define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
363 #define INTPLL_PRE_DIV_SHIFT 4
364 #define INTPLL_POST_DIV_MASK GENMASK(2, 0)
365 #define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
366 #define INTPLL_POST_DIV_SHIFT 0
368 #define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
369 #define INTPLL_LOCK_CON_DLY_SHIFT 4
370 #define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
371 #define INTPLL_LOCK_CON_OUT_SHIFT 2
372 #define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
373 #define INTPLL_LOCK_CON_IN_SHIFT 0
375 #define INTPLL_LRD_EN_MASK BIT(21)
376 #define INTPLL_FOUT_MASK BIT(20)
377 #define INTPLL_AFC_SEL_MASK BIT(19)
378 #define INTPLL_PBIAS_CTRL_MASK BIT(18)
379 #define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
380 #define INTPLL_AFCINIT_SEL_MASK BIT(16)
381 #define INTPLL_FSEL_MASK BIT(14)
382 #define INTPLL_FEED_EN_MASK BIT(13)
383 #define INTPLL_EXTAFC_MASK GENMASK(7, 3)
384 #define INTPLL_AFC_EN_MASK BIT(2)
385 #define INTPLL_ICP_MASK GENMASK(1, 0)