arch/arm/include/asm/arch-imx8m/clock.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan at nxp.com>
   6  */
   7
   8 #include <linux/bitops.h>
   9
  10 #ifdef CONFIG_IMX8MQ
  11 #include <asm/arch/clock_imx8mq.h>
  12 #elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
  13 #include <asm/arch/clock_imx8mm.h>
  14 #else
  15 #error "Error no clock.h"
  16 #endif
  17
  18 #define MHZ(X)  ((X) * 1000000UL)
  19
  20 /* Mainly for compatible to imx common code. */
  21 enum mxc_clock {
  22         MXC_ARM_CLK = 0,
  23         MXC_IPG_CLK,
  24         MXC_CSPI_CLK,
  25         MXC_ESDHC_CLK,
  26         MXC_ESDHC2_CLK,
  27         MXC_ESDHC3_CLK,
  28         MXC_I2C_CLK,
  29         MXC_UART_CLK,
  30         MXC_QSPI_CLK,
  31 };
  32
  33 enum clk_slice_type {
  34         CORE_CLOCK_SLICE,
  35         BUS_CLOCK_SLICE,
  36         IP_CLOCK_SLICE,
  37         AHB_CLOCK_SLICE,
  38         IPG_CLOCK_SLICE,
  39         CORE_SEL_CLOCK_SLICE,
  40         DRAM_SEL_CLOCK_SLICE,
  41 };
  42
  43 enum root_pre_div {
  44         CLK_ROOT_PRE_DIV1 = 0,
  45         CLK_ROOT_PRE_DIV2,
  46         CLK_ROOT_PRE_DIV3,
  47         CLK_ROOT_PRE_DIV4,
  48         CLK_ROOT_PRE_DIV5,
  49         CLK_ROOT_PRE_DIV6,
  50         CLK_ROOT_PRE_DIV7,
  51         CLK_ROOT_PRE_DIV8,
  52 };
  53
  54 enum root_post_div {
  55         CLK_ROOT_POST_DIV1 = 0,
  56         CLK_ROOT_POST_DIV2,
  57         CLK_ROOT_POST_DIV3,
  58         CLK_ROOT_POST_DIV4,
  59         CLK_ROOT_POST_DIV5,
  60         CLK_ROOT_POST_DIV6,
  61         CLK_ROOT_POST_DIV7,
  62         CLK_ROOT_POST_DIV8,
  63         CLK_ROOT_POST_DIV9,
  64         CLK_ROOT_POST_DIV10,
  65         CLK_ROOT_POST_DIV11,
  66         CLK_ROOT_POST_DIV12,
  67         CLK_ROOT_POST_DIV13,
  68         CLK_ROOT_POST_DIV14,
  69         CLK_ROOT_POST_DIV15,
  70         CLK_ROOT_POST_DIV16,
  71         CLK_ROOT_POST_DIV17,
  72         CLK_ROOT_POST_DIV18,
  73         CLK_ROOT_POST_DIV19,
  74         CLK_ROOT_POST_DIV20,
  75         CLK_ROOT_POST_DIV21,
  76         CLK_ROOT_POST_DIV22,
  77         CLK_ROOT_POST_DIV23,
  78         CLK_ROOT_POST_DIV24,
  79         CLK_ROOT_POST_DIV25,
  80         CLK_ROOT_POST_DIV26,
  81         CLK_ROOT_POST_DIV27,
  82         CLK_ROOT_POST_DIV28,
  83         CLK_ROOT_POST_DIV29,
  84         CLK_ROOT_POST_DIV30,
  85         CLK_ROOT_POST_DIV31,
  86         CLK_ROOT_POST_DIV32,
  87         CLK_ROOT_POST_DIV33,
  88         CLK_ROOT_POST_DIV34,
  89         CLK_ROOT_POST_DIV35,
  90         CLK_ROOT_POST_DIV36,
  91         CLK_ROOT_POST_DIV37,
  92         CLK_ROOT_POST_DIV38,
  93         CLK_ROOT_POST_DIV39,
  94         CLK_ROOT_POST_DIV40,
  95         CLK_ROOT_POST_DIV41,
  96         CLK_ROOT_POST_DIV42,
  97         CLK_ROOT_POST_DIV43,
  98         CLK_ROOT_POST_DIV44,
  99         CLK_ROOT_POST_DIV45,
 100         CLK_ROOT_POST_DIV46,
 101         CLK_ROOT_POST_DIV47,
 102         CLK_ROOT_POST_DIV48,
 103         CLK_ROOT_POST_DIV49,
 104         CLK_ROOT_POST_DIV50,
 105         CLK_ROOT_POST_DIV51,
 106         CLK_ROOT_POST_DIV52,
 107         CLK_ROOT_POST_DIV53,
 108         CLK_ROOT_POST_DIV54,
 109         CLK_ROOT_POST_DIV55,
 110         CLK_ROOT_POST_DIV56,
 111         CLK_ROOT_POST_DIV57,
 112         CLK_ROOT_POST_DIV58,
 113         CLK_ROOT_POST_DIV59,
 114         CLK_ROOT_POST_DIV60,
 115         CLK_ROOT_POST_DIV61,
 116         CLK_ROOT_POST_DIV62,
 117         CLK_ROOT_POST_DIV63,
 118         CLK_ROOT_POST_DIV64,
 119 };
 120
 121 struct clk_root_map {
 122         enum clk_root_index entry;
 123         enum clk_slice_type slice_type;
 124         u32 slice_index;
 125         u8 src_mux[8];
 126 };
 127
 128 struct ccm_ccgr {
 129         u32 ccgr;
 130         u32 ccgr_set;
 131         u32 ccgr_clr;
 132         u32 ccgr_tog;
 133 };
 134
 135 struct ccm_root {
 136         u32 target_root;
 137         u32 target_root_set;
 138         u32 target_root_clr;
 139         u32 target_root_tog;
 140         u32 misc;
 141         u32 misc_set;
 142         u32 misc_clr;
 143         u32 misc_tog;
 144         u32 nm_post;
 145         u32 nm_post_root_set;
 146         u32 nm_post_root_clr;
 147         u32 nm_post_root_tog;
 148         u32 nm_pre;
 149         u32 nm_pre_root_set;
 150         u32 nm_pre_root_clr;
 151         u32 nm_pre_root_tog;
 152         u32 db_post;
 153         u32 db_post_root_set;
 154         u32 db_post_root_clr;
 155         u32 db_post_root_tog;
 156         u32 db_pre;
 157         u32 db_pre_root_set;
 158         u32 db_pre_root_clr;
 159         u32 db_pre_root_tog;
 160         u32 reserved[4];
 161         u32 access_ctrl;
 162         u32 access_ctrl_root_set;
 163         u32 access_ctrl_root_clr;
 164         u32 access_ctrl_root_tog;
 165 };
 166
 167 struct ccm_reg {
 168         u32 reserved_0[4096];
 169         struct ccm_ccgr ccgr_array[192];
 170         u32 reserved_1[3328];
 171         struct ccm_root core_root[5];
 172         u32 reserved_2[352];
 173         struct ccm_root bus_root[12];
 174         u32 reserved_3[128];
 175         struct ccm_root ahb_ipg_root[4];
 176         u32 reserved_4[384];
 177         struct ccm_root dram_sel;
 178         struct ccm_root core_sel;
 179         u32 reserved_5[448];
 180         struct ccm_root ip_root[78];
 181 };
 182
 183 enum enet_freq {
 184         ENET_25MHZ = 0,
 185         ENET_50MHZ,
 186         ENET_125MHZ,
 187 };
 188
 189 #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k)                  \
 190         {                                                               \
 191                 .clk            =       (_rate),                        \
 192                 .alt_root_sel   =       (_m),                           \
 193                 .alt_pre_div    =       (_p),                           \
 194                 .apb_root_sel   =       (_s),                           \
 195                 .apb_pre_div    =       (_k),                           \
 196         }
 197
 198 struct dram_bypass_clk_setting {
 199         ulong clk;
 200         int alt_root_sel;
 201         enum root_pre_div alt_pre_div;
 202         int apb_root_sel;
 203         enum root_pre_div apb_pre_div;
 204 };
 205
 206 #define CCGR_CLK_ON_MASK        0x03
 207 #define CLK_SRC_ON_MASK         0x03
 208
 209 #define CLK_ROOT_ON             BIT(28)
 210 #define CLK_ROOT_OFF            (0 << 28)
 211 #define CLK_ROOT_ENABLE_MASK    BIT(28)
 212 #define CLK_ROOT_ENABLE_SHIFT   28
 213 #define CLK_ROOT_SOURCE_SEL(n)  (((n) & 0x7) << 24)
 214
 215 /* For SEL, only use 1 bit */
 216 #define CLK_ROOT_SRC_MUX_MASK   0x07000000
 217 #define CLK_ROOT_SRC_MUX_SHIFT  24
 218 #define CLK_ROOT_SRC_0          0x00000000
 219 #define CLK_ROOT_SRC_1          0x01000000
 220 #define CLK_ROOT_SRC_2          0x02000000
 221 #define CLK_ROOT_SRC_3          0x03000000
 222 #define CLK_ROOT_SRC_4          0x04000000
 223 #define CLK_ROOT_SRC_5          0x05000000
 224 #define CLK_ROOT_SRC_6          0x06000000
 225 #define CLK_ROOT_SRC_7          0x07000000
 226
 227 #define CLK_ROOT_PRE_DIV_MASK   (0x00070000)
 228 #define CLK_ROOT_PRE_DIV_SHIFT  16
 229 #define CLK_ROOT_PRE_DIV(n)     (((n) << 16) & 0x00070000)
 230
 231 #define CLK_ROOT_AUDO_SLOW_EN   0x1000
 232
 233 #define CLK_ROOT_AUDO_DIV_MASK  0x700
 234 #define CLK_ROOT_AUDO_DIV_SHIFT 0x8
 235 #define CLK_ROOT_AUDO_DIV(n)    (((n) << 8) & 0x700)
 236
 237 /* For CORE: mask is 0x7; For IPG: mask is 0x3 */
 238 #define CLK_ROOT_POST_DIV_MASK          0x3f
 239 #define CLK_ROOT_CORE_POST_DIV_MASK     0x7
 240 #define CLK_ROOT_IPG_POST_DIV_MASK      0x3
 241 #define CLK_ROOT_POST_DIV_SHIFT         0
 242 #define CLK_ROOT_POST_DIV(n)            ((n) & 0x3f)
 243 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK          0x01000000
 244 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK           0x02000000
 245 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK           0x03000000
 246 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK                 0x07000000
 247 #define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M                    0x01000000
 248 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK         0x01000000
 249 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK        0x01000000
 250
 251 void dram_pll_init(ulong pll_val);
 252 void dram_enable_bypass(ulong clk_val);
 253 void dram_disable_bypass(void);
 254 u32 imx_get_fecclk(void);
 255 u32 imx_get_uartclk(void);
 256 int clock_init(void);
 257 void init_clk_usdhc(u32 index);
 258 void init_uart_clk(u32 index);
 259 void init_wdog_clk(void);
 260 unsigned int mxc_get_clock(enum mxc_clock clk);
 261 int clock_enable(enum clk_ccgr_index index, bool enable);
 262 int clock_root_enabled(enum clk_root_index clock_id);
 263 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
 264                    enum root_post_div post_div, enum clk_root_src clock_src);
 265 int clock_set_target_val(enum clk_root_index clock_id, u32 val);
 266 int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
 267 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
 268 int clock_get_postdiv(enum clk_root_index clock_id,
 269                       enum root_post_div *post_div);
 270 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
 271 void mxs_set_lcdclk(u32 base_addr, u32 freq);
 272 int set_clk_qspi(void);
 273 void enable_ocotp_clk(unsigned char enable);
 274 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
 275 int set_clk_enet(enum enet_freq type);