2 * (C) Copyright 2015 Linaro
3 * Peter Griffin <peter.griffin@linaro.org>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include "hi6220_regs_alwayson.h"
13 #define HI6220_MMC0_BASE 0xF723D000
14 #define HI6220_MMC1_BASE 0xF723E000
16 #define HI6220_UART0_BASE 0xF8015000
17 #define HI6220_UART3_BASE 0xF7113000
19 #define HI6220_PMUSSI_BASE 0xF8000000
21 #define HI6220_PERI_BASE 0xF7030000
23 struct peri_sc_periph_regs {
39 u32 ddr_ctrl0; /*0x50*/
47 u32 clk0_en; /*0x200*/
53 u32 clk1_en; /*0x210*/
59 u32 clk2_en; /*0x220*/
65 u32 clk3_en; /*0x230*/
71 u32 clk8_en; /*0x240*/
77 u32 clk9_en; /*0x250*/
83 u32 clk10_en; /*0x260*/
89 u32 clk12_en; /*0x270*/
95 u32 rst0_en; /*0x300*/
101 u32 rst1_en; /*0x310*/
107 u32 rst2_en; /*0x320*/
113 u32 rst3_en; /*0x330*/
119 u32 rst8_en; /*0x340*/
125 u32 clk0_sel; /*0x400*/
129 u32 clkcfg8bit1; /*0x494*/
134 u32 reserved8_addr; /*0xd04*/
138 /* CTRL1 bit definitions */
140 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
141 #define PERI_CTRL1_HIFI_INT_MASK (1 << 1)
142 #define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2)
143 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16)
144 #define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17)
145 #define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18)
148 /* CTRL2 bit definitions */
150 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0)
151 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2)
152 #define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6)
153 #define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7)
154 #define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8)
155 #define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9)
156 #define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12)
157 #define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15)
158 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16)
159 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20)
160 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22)
161 #define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26)
162 #define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27)
163 #define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28)
165 /* CTRL3 bit definitions */
167 #define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0)
168 #define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12)
169 #define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13)
170 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14)
171 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16)
172 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18)
173 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20)
174 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22)
175 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24)
177 /* CTRL4 bit definitions */
179 #define PERI_CTRL4_PICO_FSELV (1 << 0)
180 #define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3)
181 #define PERI_CTRL4_PICO_REFCLKSEL (1 << 4)
182 #define PERI_CTRL4_PICO_SIDDQ (1 << 6)
183 #define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7)
184 #define PERI_CTRL4_PICO_OGDISABLE (1 << 8)
185 #define PERI_CTRL4_PICO_COMMONONN (1 << 9)
186 #define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10)
187 #define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11)
188 #define PERI_CTRL4_PICO_VATESTENB (1 << 12)
189 #define PERI_CTRL4_PICO_SUSPENDM (1 << 14)
190 #define PERI_CTRL4_PICO_SLEEPM (1 << 15)
191 #define PERI_CTRL4_BC11_C (1 << 16)
192 #define PERI_CTRL4_BC11_B (1 << 17)
193 #define PERI_CTRL4_BC11_A (1 << 18)
194 #define PERI_CTRL4_BC11_GND (1 << 19)
195 #define PERI_CTRL4_BC11_FLOAT (1 << 20)
196 #define PERI_CTRL4_OTG_PHY_SEL (1 << 21)
197 #define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22)
198 #define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24)
199 #define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25)
200 #define PERI_CTRL4_OTG_IDPULLUP (1 << 26)
201 #define PERI_CTRL4_OTG_DRVBUS (1 << 27)
202 #define PERI_CTRL4_OTG_SESSEND (1 << 28)
203 #define PERI_CTRL4_OTG_BVALID (1 << 29)
204 #define PERI_CTRL4_OTG_AVALID (1 << 30)
205 #define PERI_CTRL4_OTG_VBUSVALID (1 << 31)
207 /* CTRL5 bit definitions */
209 #define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)
210 #define PERI_CTRL5_PICOPHY_ACAENB (1 << 4)
211 #define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5)
212 #define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6)
213 #define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7)
214 #define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8)
215 #define PERI_CTRL5_PICOPHY_DCDENB (1 << 9)
216 #define PERI_CTRL5_PICOPHY_IDDIG (1 << 10)
217 #define PERI_CTRL5_DBG_MUX (1 << 11)
219 /* CTRL6 bit definitions */
221 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0)
222 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4)
223 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6)
224 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10)
225 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11)
226 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12)
228 /* CTRL8 bit definitions */
230 #define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0)
231 #define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2)
232 #define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4)
233 #define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6)
234 #define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8)
235 #define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11)
236 #define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12)
237 #define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16)
238 #define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20)
239 #define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28)
241 /* CTRL9 bit definitions */
243 #define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0)
244 #define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1)
245 #define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4)
246 #define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8)
248 /* CLK0 EN/DIS/STAT bit definitions */
250 #define PERI_CLK0_MMC0 (1 << 0)
251 #define PERI_CLK0_MMC1 (1 << 1)
252 #define PERI_CLK0_MMC2 (1 << 2)
253 #define PERI_CLK0_NANDC (1 << 3)
254 #define PERI_CLK0_USBOTG (1 << 4)
255 #define PERI_CLK0_PICOPHY (1 << 5)
256 #define PERI_CLK0_PLL (1 << 6)
258 /* CLK1 EN/DIS/STAT bit definitions */
260 #define PERI_CLK1_HIFI (1 << 0)
261 #define PERI_CLK1_DIGACODEC (1 << 5)
263 /* CLK2 EN/DIS/STAT bit definitions */
265 #define PERI_CLK2_IPF (1 << 0)
266 #define PERI_CLK2_SOCP (1 << 1)
267 #define PERI_CLK2_DMAC (1 << 2)
268 #define PERI_CLK2_SECENG (1 << 3)
269 #define PERI_CLK2_HPM0 (1 << 5)
270 #define PERI_CLK2_HPM1 (1 << 6)
271 #define PERI_CLK2_HPM2 (1 << 7)
272 #define PERI_CLK2_HPM3 (1 << 8)
274 /* CLK8 EN/DIS/STAT bit definitions */
276 #define PERI_CLK8_RS0 (1 << 0)
277 #define PERI_CLK8_RS2 (1 << 1)
278 #define PERI_CLK8_RS3 (1 << 2)
279 #define PERI_CLK8_MS0 (1 << 3)
280 #define PERI_CLK8_MS2 (1 << 5)
281 #define PERI_CLK8_XG2RAM0 (1 << 6)
282 #define PERI_CLK8_X2SRAM (1 << 7)
283 #define PERI_CLK8_SRAM (1 << 8)
284 #define PERI_CLK8_ROM (1 << 9)
285 #define PERI_CLK8_HARQ (1 << 10)
286 #define PERI_CLK8_MMU (1 << 11)
287 #define PERI_CLK8_DDRC (1 << 12)
288 #define PERI_CLK8_DDRPHY (1 << 13)
289 #define PERI_CLK8_DDRPHY_REF (1 << 14)
290 #define PERI_CLK8_X2X_SYSNOC (1 << 15)
291 #define PERI_CLK8_X2X_CCPU (1 << 16)
292 #define PERI_CLK8_DDRT (1 << 17)
293 #define PERI_CLK8_DDRPACK_RS (1 << 18)
295 /* CLK9 EN/DIS/STAT bit definitions */
297 #define PERI_CLK9_CARM_DAP (1 << 0)
298 #define PERI_CLK9_CARM_ATB (1 << 1)
299 #define PERI_CLK9_CARM_LBUS (1 << 2)
300 #define PERI_CLK9_CARM_KERNEL (1 << 3)
302 /* CLK10 EN/DIS/STAT bit definitions */
304 #define PERI_CLK10_IPF_CCPU (1 << 0)
305 #define PERI_CLK10_SOCP_CCPU (1 << 1)
306 #define PERI_CLK10_SECENG_CCPU (1 << 2)
307 #define PERI_CLK10_HARQ_CCPU (1 << 3)
308 #define PERI_CLK10_IPF_MCU (1 << 16)
309 #define PERI_CLK10_SOCP_MCU (1 << 17)
310 #define PERI_CLK10_SECENG_MCU (1 << 18)
311 #define PERI_CLK10_HARQ_MCU (1 << 19)
313 /* CLK12 EN/DIS/STAT bit definitions */
315 #define PERI_CLK12_HIFI_SRC (1 << 0)
316 #define PERI_CLK12_MMC0_SRC (1 << 1)
317 #define PERI_CLK12_MMC1_SRC (1 << 2)
318 #define PERI_CLK12_MMC2_SRC (1 << 3)
319 #define PERI_CLK12_SYSPLL_DIV (1 << 4)
320 #define PERI_CLK12_TPIU_SRC (1 << 5)
321 #define PERI_CLK12_MMC0_HF (1 << 6)
322 #define PERI_CLK12_MMC1_HF (1 << 7)
323 #define PERI_CLK12_PLL_TEST_SRC (1 << 8)
324 #define PERI_CLK12_CODEC_SOC (1 << 9)
325 #define PERI_CLK12_MEDIA (1 << 10)
327 /* RST0 EN/DIS/STAT bit definitions */
329 #define PERI_RST0_MMC0 (1 << 0)
330 #define PERI_RST0_MMC1 (1 << 1)
331 #define PERI_RST0_MMC2 (1 << 2)
332 #define PERI_RST0_NANDC (1 << 3)
333 #define PERI_RST0_USBOTG_BUS (1 << 4)
334 #define PERI_RST0_POR_PICOPHY (1 << 5)
335 #define PERI_RST0_USBOTG (1 << 6)
336 #define PERI_RST0_USBOTG_32K (1 << 7)
338 /* RST1 EN/DIS/STAT bit definitions */
340 #define PERI_RST1_HIFI (1 << 0)
341 #define PERI_RST1_DIGACODEC (1 << 5)
343 /* RST2 EN/DIS/STAT bit definitions */
345 #define PERI_RST2_IPF (1 << 0)
346 #define PERI_RST2_SOCP (1 << 1)
347 #define PERI_RST2_DMAC (1 << 2)
348 #define PERI_RST2_SECENG (1 << 3)
349 #define PERI_RST2_ABB (1 << 4)
350 #define PERI_RST2_HPM0 (1 << 5)
351 #define PERI_RST2_HPM1 (1 << 6)
352 #define PERI_RST2_HPM2 (1 << 7)
353 #define PERI_RST2_HPM3 (1 << 8)
355 /* RST3 EN/DIS/STAT bit definitions */
357 #define PERI_RST3_CSSYS (1 << 0)
358 #define PERI_RST3_I2C0 (1 << 1)
359 #define PERI_RST3_I2C1 (1 << 2)
360 #define PERI_RST3_I2C2 (1 << 3)
361 #define PERI_RST3_I2C3 (1 << 4)
362 #define PERI_RST3_UART1 (1 << 5)
363 #define PERI_RST3_UART2 (1 << 6)
364 #define PERI_RST3_UART3 (1 << 7)
365 #define PERI_RST3_UART4 (1 << 8)
366 #define PERI_RST3_SSP (1 << 9)
367 #define PERI_RST3_PWM (1 << 10)
368 #define PERI_RST3_BLPWM (1 << 11)
369 #define PERI_RST3_TSENSOR (1 << 12)
370 #define PERI_RST3_DAPB (1 << 18)
371 #define PERI_RST3_HKADC (1 << 19)
372 #define PERI_RST3_CODEC (1 << 20)
374 /* RST8 EN/DIS/STAT bit definitions */
376 #define PERI_RST8_RS0 (1 << 0)
377 #define PERI_RST8_RS2 (1 << 1)
378 #define PERI_RST8_RS3 (1 << 2)
379 #define PERI_RST8_MS0 (1 << 3)
380 #define PERI_RST8_MS2 (1 << 5)
381 #define PERI_RST8_XG2RAM0 (1 << 6)
382 #define PERI_RST8_X2SRAM_TZMA (1 << 7)
383 #define PERI_RST8_SRAM (1 << 8)
384 #define PERI_RST8_HARQ (1 << 10)
385 #define PERI_RST8_DDRC (1 << 12)
386 #define PERI_RST8_DDRC_APB (1 << 13)
387 #define PERI_RST8_DDRPACK_APB (1 << 14)
388 #define PERI_RST8_DDRT (1 << 17)
390 #endif /*__HI62220_H__*/