arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2017 Linaro
   4  * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
   5  */
   6
   7 #ifndef __HI3798cv200_H__
   8 #define __HI3798cv200_H__
   9
  10 #define REG_BASE_PERI_CTRL              0xF8A20000
  11 #define REG_BASE_CRG                    0xF8A22000
  12
  13 /* DEVICES */
  14 #define REG_BASE_UART0                  0xF8B00000
  15 #define HIOTG_BASE_ADDR                 0xF98C0000
  16
  17 /* PERI control registers (4KB) */
  18         /* USB2 PHY01 configuration register */
  19 #define PERI_CTRL_USB0                  (REG_BASE_PERI_CTRL + 0x120)
  20
  21         /* USB2 controller configuration register */
  22 #define PERI_CTRL_USB3                  (REG_BASE_PERI_CTRL + 0x12c)
  23 #define USB2_2P_CHIPID                  (1 << 28)
  24
  25 /* PERI CRG registers (4KB) */
  26         /* USB2 CTRL0 clock and soft reset */
  27 #define PERI_CRG46                      (REG_BASE_CRG + 0xb8)
  28 #define USB2_BUS_CKEN                   (1<<0)
  29 #define USB2_OHCI48M_CKEN               (1<<1)
  30 #define USB2_OHCI12M_CKEN               (1<<2)
  31 #define USB2_OTG_UTMI_CKEN              (1<<3)
  32 #define USB2_HST_PHY_CKEN               (1<<4)
  33 #define USB2_UTMI0_CKEN                 (1<<5)
  34 #define USB2_BUS_SRST_REQ               (1<<12)
  35 #define USB2_UTMI0_SRST_REQ             (1<<13)
  36 #define USB2_HST_PHY_SYST_REQ           (1<<16)
  37 #define USB2_OTG_PHY_SYST_REQ           (1<<17)
  38 #define USB2_CLK48_SEL                  (1<<20)
  39
  40         /* USB2 PHY clock and soft reset */
  41 #define PERI_CRG47                      (REG_BASE_CRG + 0xbc)
  42 #define USB2_PHY01_REF_CKEN             (1 << 0)
  43 #define USB2_PHY2_REF_CKEN              (1 << 2)
  44 #define USB2_PHY01_SRST_REQ             (1 << 4)
  45 #define USB2_PHY2_SRST_REQ              (1 << 6)
  46 #define USB2_PHY01_SRST_TREQ0           (1 << 8)
  47 #define USB2_PHY01_SRST_TREQ1           (1 << 9)
  48 #define USB2_PHY2_SRST_TREQ             (1 << 10)
  49 #define USB2_PHY01_REFCLK_SEL           (1 << 12)
  50 #define USB2_PHY2_REFCLK_SEL            (1 << 14)
  51
  52
  53 #endif