1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
7 #ifndef __HI3798cv200_H__
8 #define __HI3798cv200_H__
10 #define REG_BASE_PERI_CTRL 0xF8A20000
11 #define REG_BASE_CRG 0xF8A22000
14 #define REG_BASE_MCI 0xF9830000
15 #define REG_BASE_UART0 0xF8B00000
16 #define HIOTG_BASE_ADDR 0xF98C0000
18 /* PERI control registers (4KB) */
19 /* USB2 PHY01 configuration register */
20 #define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120)
22 /* USB2 controller configuration register */
23 #define PERI_CTRL_USB3 (REG_BASE_PERI_CTRL + 0x12c)
24 #define USB2_2P_CHIPID (1 << 28)
26 /* PERI CRG registers (4KB) */
27 /* USB2 CTRL0 clock and soft reset */
28 #define PERI_CRG46 (REG_BASE_CRG + 0xb8)
29 #define USB2_BUS_CKEN (1<<0)
30 #define USB2_OHCI48M_CKEN (1<<1)
31 #define USB2_OHCI12M_CKEN (1<<2)
32 #define USB2_OTG_UTMI_CKEN (1<<3)
33 #define USB2_HST_PHY_CKEN (1<<4)
34 #define USB2_UTMI0_CKEN (1<<5)
35 #define USB2_BUS_SRST_REQ (1<<12)
36 #define USB2_UTMI0_SRST_REQ (1<<13)
37 #define USB2_HST_PHY_SYST_REQ (1<<16)
38 #define USB2_OTG_PHY_SYST_REQ (1<<17)
39 #define USB2_CLK48_SEL (1<<20)
41 /* USB2 PHY clock and soft reset */
42 #define PERI_CRG47 (REG_BASE_CRG + 0xbc)
43 #define USB2_PHY01_REF_CKEN (1 << 0)
44 #define USB2_PHY2_REF_CKEN (1 << 2)
45 #define USB2_PHY01_SRST_REQ (1 << 4)
46 #define USB2_PHY2_SRST_REQ (1 << 6)
47 #define USB2_PHY01_SRST_TREQ0 (1 << 8)
48 #define USB2_PHY01_SRST_TREQ1 (1 << 9)
49 #define USB2_PHY2_SRST_TREQ (1 << 10)
50 #define USB2_PHY01_REFCLK_SEL (1 << 12)
51 #define USB2_PHY2_REFCLK_SEL (1 << 14)