arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h

   1 /*
   2  * LayerScape Internal Memory Map
   3  *
   4  * Copyright 2014 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H
  10 #define __ARCH_FSL_LSCH3_IMMAP_H_
  11
  12 /* This is chassis generation 3 */
  13
  14 struct sys_info {
  15         unsigned long freq_processor[CONFIG_MAX_CPUS];
  16         unsigned long freq_systembus;
  17         unsigned long freq_ddrbus;
  18         unsigned long freq_ddrbus2;
  19         unsigned long freq_localbus;
  20         unsigned long freq_qe;
  21 #ifdef CONFIG_SYS_DPAA_FMAN
  22         unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
  23 #endif
  24 #ifdef CONFIG_SYS_DPAA_QBMAN
  25         unsigned long freq_qman;
  26 #endif
  27 #ifdef CONFIG_SYS_DPAA_PME
  28         unsigned long freq_pme;
  29 #endif
  30 };
  31
  32 /* Global Utilities Block */
  33 struct ccsr_gur {
  34         u32     porsr1;         /* POR status 1 */
  35         u32     porsr2;         /* POR status 2 */
  36         u8      res_008[0x20-0x8];
  37         u32     gpporcr1;       /* General-purpose POR configuration */
  38         u32     gpporcr2;       /* General-purpose POR configuration 2 */
  39         u32     dcfg_fusesr;    /* Fuse status register */
  40         u32     gpporcr3;
  41         u32     gpporcr4;
  42         u8      res_034[0x70-0x34];
  43         u32     devdisr;        /* Device disable control */
  44         u32     devdisr2;       /* Device disable control 2 */
  45         u32     devdisr3;       /* Device disable control 3 */
  46         u32     devdisr4;       /* Device disable control 4 */
  47         u32     devdisr5;       /* Device disable control 5 */
  48         u32     devdisr6;       /* Device disable control 6 */
  49         u32     devdisr7;       /* Device disable control 7 */
  50 #define FSL_CHASSIS3_DEVDISR2_DPMAC1    0x00000001
  51 #define FSL_CHASSIS3_DEVDISR2_DPMAC2    0x00000002
  52 #define FSL_CHASSIS3_DEVDISR2_DPMAC3    0x00000004
  53 #define FSL_CHASSIS3_DEVDISR2_DPMAC4    0x00000008
  54 #define FSL_CHASSIS3_DEVDISR2_DPMAC5    0x00000010
  55 #define FSL_CHASSIS3_DEVDISR2_DPMAC6    0x00000020
  56 #define FSL_CHASSIS3_DEVDISR2_DPMAC7    0x00000040
  57 #define FSL_CHASSIS3_DEVDISR2_DPMAC8    0x00000080
  58 #define FSL_CHASSIS3_DEVDISR2_DPMAC9    0x00000100
  59 #define FSL_CHASSIS3_DEVDISR2_DPMAC10   0x00000200
  60 #define FSL_CHASSIS3_DEVDISR2_DPMAC11   0x00000400
  61 #define FSL_CHASSIS3_DEVDISR2_DPMAC12   0x00000800
  62 #define FSL_CHASSIS3_DEVDISR2_DPMAC13   0x00001000
  63 #define FSL_CHASSIS3_DEVDISR2_DPMAC14   0x00002000
  64 #define FSL_CHASSIS3_DEVDISR2_DPMAC15   0x00004000
  65 #define FSL_CHASSIS3_DEVDISR2_DPMAC16   0x00008000
  66 #define FSL_CHASSIS3_DEVDISR2_DPMAC17   0x00010000
  67 #define FSL_CHASSIS3_DEVDISR2_DPMAC18   0x00020000
  68 #define FSL_CHASSIS3_DEVDISR2_DPMAC19   0x00040000
  69 #define FSL_CHASSIS3_DEVDISR2_DPMAC20   0x00080000
  70 #define FSL_CHASSIS3_DEVDISR2_DPMAC21   0x00100000
  71 #define FSL_CHASSIS3_DEVDISR2_DPMAC22   0x00200000
  72 #define FSL_CHASSIS3_DEVDISR2_DPMAC23   0x00400000
  73 #define FSL_CHASSIS3_DEVDISR2_DPMAC24   0x00800000
  74         u8      res_08c[0x90-0x8c];
  75         u32     coredisru;      /* uppper portion for support of 64 cores */
  76         u32     coredisrl;      /* lower portion for support of 64 cores */
  77         u8      res_098[0xa0-0x98];
  78         u32     pvr;            /* Processor version */
  79         u32     svr;            /* System version */
  80         u32     mvr;            /* Manufacturing version */
  81         u8      res_0ac[0x100-0xac];
  82         u32     rcwsr[32];      /* Reset control word status */
  83
  84 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT   2
  85 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK    0x1f
  86 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT   10
  87 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK    0x3f
  88 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT  18
  89 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK   0x3f
  90 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x00FF0000
  91 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
  92 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
  93 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
  94
  95         u8      res_180[0x200-0x180];
  96         u32     scratchrw[32];  /* Scratch Read/Write */
  97         u8      res_280[0x300-0x280];
  98         u32     scratchw1r[4];  /* Scratch Read (Write once) */
  99         u8      res_310[0x400-0x310];
 100         u32     bootlocptrl;    /* Boot location pointer low-order addr */
 101         u32     bootlocptrh;    /* Boot location pointer high-order addr */
 102         u8      res_408[0x500-0x408];
 103         u8      res_500[0x740-0x500];   /* add more registers when needed */
 104         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 105         struct {
 106                 u32     upper;
 107                 u32     lower;
 108         } tp_cluster[3];        /* Core Cluster n Topology Register */
 109         u8      res_858[0x1000-0x858];
 110 };
 111
 112 #define TP_ITYP_AV              0x00000001      /* Initiator available */
 113 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
 114 #define TP_ITYP_TYPE_ARM        0x0
 115 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
 116 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
 117 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
 118 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
 119 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
 120 #define TY_ITYP_VER_A7          0x1
 121 #define TY_ITYP_VER_A53         0x2
 122 #define TY_ITYP_VER_A57         0x3
 123
 124 #define TP_CLUSTER_EOC          0x80000000      /* end of clusters */
 125 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 126 #define TP_INIT_PER_CLUSTER     4
 127
 128 struct ccsr_clk_cluster_group {
 129         struct {
 130                 u8      res_00[0x10];
 131                 u32     csr;
 132                 u8      res_14[0x20-0x14];
 133         } hwncsr[3];
 134         u8      res_60[0x80-0x60];
 135         struct {
 136                 u32     gsr;
 137                 u8      res_84[0xa0-0x84];
 138         } pllngsr[3];
 139         u8      res_e0[0x100-0xe0];
 140 };
 141
 142 struct ccsr_clk_ctrl {
 143         struct {
 144                 u32 csr;        /* core cluster n clock control status */
 145                 u8  res_04[0x20-0x04];
 146         } clkcncsr[8];
 147 };
 148
 149 struct ccsr_reset {
 150         u32 rstcr;                      /* 0x000 */
 151         u32 rstcrsp;                    /* 0x004 */
 152         u8 res_008[0x10-0x08];          /* 0x008 */
 153         u32 rstrqmr1;                   /* 0x010 */
 154         u32 rstrqmr2;                   /* 0x014 */
 155         u32 rstrqsr1;                   /* 0x018 */
 156         u32 rstrqsr2;                   /* 0x01c */
 157         u32 rstrqwdtmrl;                /* 0x020 */
 158         u32 rstrqwdtmru;                /* 0x024 */
 159         u8 res_028[0x30-0x28];          /* 0x028 */
 160         u32 rstrqwdtsrl;                /* 0x030 */
 161         u32 rstrqwdtsru;                /* 0x034 */
 162         u8 res_038[0x60-0x38];          /* 0x038 */
 163         u32 brrl;                       /* 0x060 */
 164         u32 brru;                       /* 0x064 */
 165         u8 res_068[0x80-0x68];          /* 0x068 */
 166         u32 pirset;                     /* 0x080 */
 167         u32 pirclr;                     /* 0x084 */
 168         u8 res_088[0x90-0x88];          /* 0x088 */
 169         u32 brcorenbr;                  /* 0x090 */
 170         u8 res_094[0x100-0x94];         /* 0x094 */
 171         u32 rcw_reqr;                   /* 0x100 */
 172         u32 rcw_completion;             /* 0x104 */
 173         u8 res_108[0x110-0x108];        /* 0x108 */
 174         u32 pbi_reqr;                   /* 0x110 */
 175         u32 pbi_completion;             /* 0x114 */
 176         u8 res_118[0xa00-0x118];        /* 0x118 */
 177         u32 qmbm_warmrst;               /* 0xa00 */
 178         u32 soc_warmrst;                /* 0xa04 */
 179         u8 res_a08[0xbf8-0xa08];        /* 0xa08 */
 180         u32 ip_rev1;                    /* 0xbf8 */
 181         u32 ip_rev2;                    /* 0xbfc */
 182 };
 183 #endif /* __ARCH_FSL_LSCH3_IMMAP_H */