arch/arm/include/asm/arch-fsl-lsch3/config.h

   1 /*
   2  * Copyright 2014, Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
   8 #define _ASM_ARMV8_FSL_LSCH3_CONFIG_
   9
  10 #include <fsl_ddrc_version.h>
  11
  12 #define CONFIG_SYS_PAGE_SIZE            0x10000
  13
  14 #ifndef L1_CACHE_BYTES
  15 #define L1_CACHE_SHIFT          6
  16 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  17 #endif
  18
  19 #define CONFIG_MP
  20 #define CONFIG_SYS_FSL_OCRAM_BASE       0x18000000      /* initial RAM */
  21 /* Link Definitions */
  22 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  23
  24 #define CONFIG_SYS_IMMR                         0x01000000
  25 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
  26 #define CONFIG_SYS_FSL_DDR2_ADDR                (CONFIG_SYS_IMMR + 0x00090000)
  27 #define CONFIG_SYS_FSL_DDR3_ADDR                0x08210000
  28 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00E00000)
  29 #define CONFIG_SYS_FSL_PMU_ADDR                 (CONFIG_SYS_IMMR + 0x00E30000)
  30 #define CONFIG_SYS_FSL_RST_ADDR                 (CONFIG_SYS_IMMR + 0x00E60000)
  31 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR        (CONFIG_SYS_IMMR + 0x00300000)
  32 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR        (CONFIG_SYS_IMMR + 0x00310000)
  33 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR        (CONFIG_SYS_IMMR + 0x00370000)
  34 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x01240000)
  35 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011C0500)
  36 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011C0600)
  37 #define CONFIG_SYS_FSL_TIMER_ADDR               0x023d0000
  38 #define CONFIG_SYS_FSL_PMU_CLTBENR              (CONFIG_SYS_FSL_PMU_ADDR + \
  39                                                  0x18A0)
  40
  41 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR        (CONFIG_SYS_IMMR + 0xEA0000)
  42
  43 /* SP (Cortex-A5) related */
  44 #define CONFIG_SYS_FSL_SP_ADDR                  (CONFIG_SYS_IMMR + 0x00F00000)
  45 #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR          (CONFIG_SYS_FSL_SP_ADDR)
  46 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1         (CONFIG_SYS_FSL_SP_ADDR)
  47 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2         \
  48                                         (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
  49 #define CONFIG_SYS_FSL_SP_LOOPBACK_DUART        \
  50                                         (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
  51
  52 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR            0x70012c000ULL
  53 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR           0x70012d000ULL
  54 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR           0x700132000ULL
  55 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR           0x700133000ULL
  56
  57 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01000000)
  58 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01010000)
  59 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01020000)
  60 #define I2C4_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01030000)
  61
  62 /* TZ Protection Controller Definitions */
  63 #define TZPC_BASE                               0x02200000
  64 #define TZPCR0SIZE_BASE                         (TZPC_BASE)
  65 #define TZPCDECPROT_0_STAT_BASE                 (TZPC_BASE + 0x800)
  66 #define TZPCDECPROT_0_SET_BASE                  (TZPC_BASE + 0x804)
  67 #define TZPCDECPROT_0_CLR_BASE                  (TZPC_BASE + 0x808)
  68 #define TZPCDECPROT_1_STAT_BASE                 (TZPC_BASE + 0x80C)
  69 #define TZPCDECPROT_1_SET_BASE                  (TZPC_BASE + 0x810)
  70 #define TZPCDECPROT_1_CLR_BASE                  (TZPC_BASE + 0x814)
  71 #define TZPCDECPROT_2_STAT_BASE                 (TZPC_BASE + 0x818)
  72 #define TZPCDECPROT_2_SET_BASE                  (TZPC_BASE + 0x81C)
  73 #define TZPCDECPROT_2_CLR_BASE                  (TZPC_BASE + 0x820)
  74
  75 /* TZ Address Space Controller Definitions */
  76 #define TZASC1_BASE                     0x01100000      /* as per CCSR map. */
  77 #define TZASC2_BASE                     0x01110000      /* as per CCSR map. */
  78 #define TZASC3_BASE                     0x01120000      /* as per CCSR map. */
  79 #define TZASC4_BASE                     0x01130000      /* as per CCSR map. */
  80 #define TZASC_BUILD_CONFIG_REG(x)       ((TZASC1_BASE + (x * 0x10000)))
  81 #define TZASC_ACTION_REG(x)             ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  82 #define TZASC_GATE_KEEPER(x)            ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  83 #define TZASC_REGION_BASE_LOW_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  84 #define TZASC_REGION_BASE_HIGH_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  85 #define TZASC_REGION_TOP_LOW_0(x)       ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  86 #define TZASC_REGION_TOP_HIGH_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  87 #define TZASC_REGION_ATTRIBUTES_0(x)    ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  88 #define TZASC_REGION_ID_ACCESS_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  89
  90 /* Generic Interrupt Controller Definitions */
  91 #define GICD_BASE               0x06000000
  92 #define GICR_BASE               0x06100000
  93
  94 /* SMMU Defintions */
  95 #define SMMU_BASE               0x05000000 /* GR0 Base */
  96
  97 /* DDR */
  98 #define CONFIG_SYS_FSL_DDR_LE
  99 #define CONFIG_VERY_BIG_RAM
 100 #ifdef CONFIG_SYS_FSL_DDR4
 101 #define CONFIG_SYS_FSL_DDRC_GEN4
 102 #else
 103 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3    /* Enable Freescale ARM DDR3 driver */
 104 #endif
 105 #define CONFIG_SYS_FSL_DDR              /* Freescale DDR driver */
 106 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 107 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 108 #define CONFIG_SYS_FSL_DDR_VER          FSL_DDR_VER_5_0
 109
 110 /* IFC */
 111 #define CONFIG_SYS_FSL_IFC_LE
 112
 113 /* PCIe */
 114 #define CONFIG_SYS_PCIE1_ADDR                   (CONFIG_SYS_IMMR + 0x2400000)
 115 #define CONFIG_SYS_PCIE2_ADDR                   (CONFIG_SYS_IMMR + 0x2500000)
 116 #define CONFIG_SYS_PCIE3_ADDR                   (CONFIG_SYS_IMMR + 0x2600000)
 117 #define CONFIG_SYS_PCIE4_ADDR                   (CONFIG_SYS_IMMR + 0x2700000)
 118 #define CONFIG_SYS_PCIE1_PHYS_ADDR              0x1000000000ULL
 119 #define CONFIG_SYS_PCIE2_PHYS_ADDR              0x1200000000ULL
 120 #define CONFIG_SYS_PCIE3_PHYS_ADDR              0x1400000000ULL
 121 #define CONFIG_SYS_PCIE4_PHYS_ADDR              0x1600000000ULL
 122
 123 /* Cache Coherent Interconnect */
 124 #define CCI_MN_BASE             0x04000000
 125 #define CCI_MN_RNF_NODEID_LIST          0x180
 126 #define CCI_MN_DVM_DOMAIN_CTL           0x200
 127 #define CCI_MN_DVM_DOMAIN_CTL_SET       0x210
 128
 129 /* Supplemental Configuration */
 130 #define SCFG_BASE               0x01fc0000
 131 #define SCFG_USB3PRM1CR                 0x000
 132
 133 #ifdef CONFIG_LS2085A
 134 #define CONFIG_MAX_CPUS                         16
 135 #define CONFIG_SYS_FSL_IFC_BANK_COUNT           8
 136 #define CONFIG_NUM_DDR_CONTROLLERS              3
 137 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS           { 1, 1, 4, 4 }
 138 #define CONFIG_SYS_FSL_SRDS_1
 139 #define CONFIG_SYS_FSL_SRDS_2
 140 #else
 141 #error SoC not defined
 142 #endif
 143
 144 #ifdef CONFIG_LS2085A
 145 #define CONFIG_SYS_FSL_ERRATUM_A008336
 146 #define CONFIG_SYS_FSL_ERRATUM_A008511
 147 #define CONFIG_SYS_FSL_ERRATUM_A008514
 148 #define CONFIG_SYS_FSL_ERRATUM_A008585
 149 #define CONFIG_SYS_FSL_ERRATUM_A008751
 150 #endif
 151
 152 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */