1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2015 Freescale Semiconductor
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
11 #include <linux/types.h>
12 #ifdef CONFIG_FSL_LSCH2
13 #include <asm/arch/immap_lsch2.h>
15 #ifdef CONFIG_FSL_LSCH3
16 #include <asm/arch/immap_lsch3.h>
20 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
21 #define gur_in32(a) in_le32(a)
22 #define gur_out32(a, v) out_le32(a, v)
23 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
24 #define gur_in32(a) in_be32(a)
25 #define gur_out32(a, v) out_be32(a, v)
28 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
29 #define scfg_in32(a) in_le32(a)
30 #define scfg_out32(a, v) out_le32(a, v)
31 #define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
32 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
33 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
34 #define scfg_in32(a) in_be32(a)
35 #define scfg_out32(a, v) out_be32(a, v)
36 #define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
37 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
40 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE
41 #define pex_lut_in32(a) in_le32(a)
42 #define pex_lut_out32(a, v) out_le32(a, v)
43 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
44 #define pex_lut_in32(a) in_be32(a)
45 #define pex_lut_out32(a, v) out_be32(a, v)
54 #define CPU_TYPE_ENTRY(n, v, nc) \
55 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
58 #define SMC_DRAM_BANK_INFO (0xC200FF12)
59 #define SIP_SVC_RCW 0xC200FF18
61 phys_size_t tfa_get_dram_size(void);
64 BOOT_SOURCE_RESERVED = 0,
68 BOOT_SOURCE_QSPI_NAND,
70 BOOT_SOURCE_XSPI_NAND,
73 BOOT_SOURCE_I2C1_EXTENDED,
76 enum boot_src get_boot_src(void);
79 #define SVR_WO_E 0xFFFFFE
80 #define SVR_LS1012A 0x870400
81 #define SVR_LS1043A 0x879200
82 #define SVR_LS1023A 0x879208
83 #define SVR_LS1046A 0x870700
84 #define SVR_LS1026A 0x870708
85 #define SVR_LS1048A 0x870320
86 #define SVR_LS1084A 0x870302
87 #define SVR_LS1088A 0x870300
88 #define SVR_LS1044A 0x870322
89 #define SVR_LS2045A 0x870120
90 #define SVR_LS2080A 0x870110
91 #define SVR_LS2085A 0x870100
92 #define SVR_LS2040A 0x870130
93 #define SVR_LS2088A 0x870900
94 #define SVR_LS2084A 0x870910
95 #define SVR_LS2048A 0x870920
96 #define SVR_LS2044A 0x870930
97 #define SVR_LS2081A 0x870918
98 #define SVR_LS2041A 0x870914
100 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
101 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
102 #define SVR_REV(svr) (((svr) >> 0) & 0xff)
103 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
104 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
105 #define IS_SVR_REV(svr, maj, min) \
106 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
107 #define SVR_DEV(svr) ((svr) >> 8)
108 #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
111 #ifdef CONFIG_FSL_LSCH3
112 void fsl_lsch3_early_init_f(void);
113 int get_core_volt_from_fuse(void);
114 #elif defined(CONFIG_FSL_LSCH2)
115 void fsl_lsch2_early_init_f(void);
116 int setup_chip_volt(void);
117 /* Setup core vdd in unit mV */
118 int board_setup_core_volt(u32 vdd);
119 #ifdef CONFIG_FSL_PFE
120 void init_pfe_scfg_dcfg_regs(void);
123 #ifdef CONFIG_QSPI_AHB_INIT
124 int qspi_ahb_init(void);
127 void cpu_name(char *name);
128 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
129 void erratum_a009635(void);
132 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
133 void erratum_a010315(void);
136 bool soc_has_dp_ddr(void);
137 bool soc_has_aiop(void);
140 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */