arch/arm/include/asm/arch-fsl-layerscape/ns_access.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_NS_ACCESS_H_
   8 #define __FSL_NS_ACCESS_H_
   9 #include <fsl_csu.h>
  10
  11 enum csu_cslx_ind {
  12         CSU_CSLX_PCIE2_IO = 0,
  13         CSU_CSLX_PCIE1_IO,
  14         CSU_CSLX_MG2TPR_IP,
  15         CSU_CSLX_IFC_MEM,
  16         CSU_CSLX_OCRAM,
  17         CSU_CSLX_GIC,
  18         CSU_CSLX_PCIE1,
  19         CSU_CSLX_OCRAM2,
  20         CSU_CSLX_QSPI_MEM,
  21         CSU_CSLX_PCIE2,
  22         CSU_CSLX_SATA,
  23         CSU_CSLX_USB1,
  24         CSU_CSLX_QM_BM_SWPORTAL,
  25         CSU_CSLX_PCIE3 = 16,
  26         CSU_CSLX_PCIE3_IO,
  27         CSU_CSLX_USB3 = 20,
  28         CSU_CSLX_USB2,
  29         CSU_CSLX_SERDES = 32,
  30         CSU_CSLX_QDMA,
  31         CSU_CSLX_LPUART2,
  32         CSU_CSLX_LPUART1,
  33         CSU_CSLX_LPUART4,
  34         CSU_CSLX_LPUART3,
  35         CSU_CSLX_LPUART6,
  36         CSU_CSLX_LPUART5,
  37         CSU_CSLX_DSPI1 = 41,
  38         CSU_CSLX_QSPI,
  39         CSU_CSLX_ESDHC,
  40         CSU_CSLX_IFC = 45,
  41         CSU_CSLX_I2C1,
  42         CSU_CSLX_I2C3 = 48,
  43         CSU_CSLX_I2C2,
  44         CSU_CSLX_DUART2 = 50,
  45         CSU_CSLX_DUART1,
  46         CSU_CSLX_WDT2,
  47         CSU_CSLX_WDT1,
  48         CSU_CSLX_EDMA,
  49         CSU_CSLX_SYS_CNT,
  50         CSU_CSLX_DMA_MUX2,
  51         CSU_CSLX_DMA_MUX1,
  52         CSU_CSLX_DDR,
  53         CSU_CSLX_QUICC,
  54         CSU_CSLX_DCFG_CCU_RCPM = 60,
  55         CSU_CSLX_SECURE_BOOTROM,
  56         CSU_CSLX_SFP,
  57         CSU_CSLX_TMU,
  58         CSU_CSLX_SECURE_MONITOR,
  59         CSU_CSLX_SCFG,
  60         CSU_CSLX_FM = 66,
  61         CSU_CSLX_SEC5_5,
  62         CSU_CSLX_BM,
  63         CSU_CSLX_QM,
  64         CSU_CSLX_GPIO2 = 70,
  65         CSU_CSLX_GPIO1,
  66         CSU_CSLX_GPIO4,
  67         CSU_CSLX_GPIO3,
  68         CSU_CSLX_PLATFORM_CONT,
  69         CSU_CSLX_CSU,
  70         CSU_CSLX_IIC4 = 77,
  71         CSU_CSLX_WDT4,
  72         CSU_CSLX_WDT3,
  73         CSU_CSLX_ESDHC2 = 80,
  74         CSU_CSLX_WDT5 = 81,
  75         CSU_CSLX_SAI2,
  76         CSU_CSLX_SAI1,
  77         CSU_CSLX_SAI4,
  78         CSU_CSLX_SAI3,
  79         CSU_CSLX_FTM2 = 86,
  80         CSU_CSLX_FTM1,
  81         CSU_CSLX_FTM4,
  82         CSU_CSLX_FTM3,
  83         CSU_CSLX_FTM6 = 90,
  84         CSU_CSLX_FTM5,
  85         CSU_CSLX_FTM8,
  86         CSU_CSLX_FTM7,
  87         CSU_CSLX_DSCR = 121,
  88 };
  89
  90 static struct csu_ns_dev ns_dev[] = {
  91          {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
  92          {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
  93          {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
  94          {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
  95          {CSU_CSLX_OCRAM, CSU_ALL_RW},
  96          {CSU_CSLX_GIC, CSU_ALL_RW},
  97          {CSU_CSLX_PCIE1, CSU_ALL_RW},
  98          {CSU_CSLX_OCRAM2, CSU_ALL_RW},
  99          {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
 100          {CSU_CSLX_PCIE2, CSU_ALL_RW},
 101          {CSU_CSLX_SATA, CSU_ALL_RW},
 102          {CSU_CSLX_USB1, CSU_ALL_RW},
 103          {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
 104          {CSU_CSLX_PCIE3, CSU_ALL_RW},
 105          {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
 106          {CSU_CSLX_USB3, CSU_ALL_RW},
 107          {CSU_CSLX_USB2, CSU_ALL_RW},
 108          {CSU_CSLX_SERDES, CSU_ALL_RW},
 109          {CSU_CSLX_QDMA, CSU_ALL_RW},
 110          {CSU_CSLX_LPUART2, CSU_ALL_RW},
 111          {CSU_CSLX_LPUART1, CSU_ALL_RW},
 112          {CSU_CSLX_LPUART4, CSU_ALL_RW},
 113          {CSU_CSLX_LPUART3, CSU_ALL_RW},
 114          {CSU_CSLX_LPUART6, CSU_ALL_RW},
 115          {CSU_CSLX_LPUART5, CSU_ALL_RW},
 116          {CSU_CSLX_DSPI1, CSU_ALL_RW},
 117          {CSU_CSLX_QSPI, CSU_ALL_RW},
 118          {CSU_CSLX_ESDHC, CSU_ALL_RW},
 119          {CSU_CSLX_IFC, CSU_ALL_RW},
 120          {CSU_CSLX_I2C1, CSU_ALL_RW},
 121          {CSU_CSLX_I2C3, CSU_ALL_RW},
 122          {CSU_CSLX_I2C2, CSU_ALL_RW},
 123          {CSU_CSLX_DUART2, CSU_ALL_RW},
 124          {CSU_CSLX_DUART1, CSU_ALL_RW},
 125          {CSU_CSLX_WDT2, CSU_ALL_RW},
 126          {CSU_CSLX_WDT1, CSU_ALL_RW},
 127          {CSU_CSLX_EDMA, CSU_ALL_RW},
 128          {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
 129          {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
 130          {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
 131          {CSU_CSLX_DDR, CSU_ALL_RW},
 132          {CSU_CSLX_QUICC, CSU_ALL_RW},
 133          {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
 134          {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
 135          {CSU_CSLX_SFP, CSU_ALL_RW},
 136          {CSU_CSLX_TMU, CSU_ALL_RW},
 137          {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
 138          {CSU_CSLX_SCFG, CSU_ALL_RW},
 139          {CSU_CSLX_FM, CSU_ALL_RW},
 140          {CSU_CSLX_SEC5_5, CSU_ALL_RW},
 141          {CSU_CSLX_BM, CSU_ALL_RW},
 142          {CSU_CSLX_QM, CSU_ALL_RW},
 143          {CSU_CSLX_GPIO2, CSU_ALL_RW},
 144          {CSU_CSLX_GPIO1, CSU_ALL_RW},
 145          {CSU_CSLX_GPIO4, CSU_ALL_RW},
 146          {CSU_CSLX_GPIO3, CSU_ALL_RW},
 147          {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
 148          {CSU_CSLX_CSU, CSU_ALL_RW},
 149          {CSU_CSLX_IIC4, CSU_ALL_RW},
 150          {CSU_CSLX_WDT4, CSU_ALL_RW},
 151          {CSU_CSLX_WDT3, CSU_ALL_RW},
 152          {CSU_CSLX_ESDHC2, CSU_ALL_RW},
 153          {CSU_CSLX_WDT5, CSU_ALL_RW},
 154          {CSU_CSLX_SAI2, CSU_ALL_RW},
 155          {CSU_CSLX_SAI1, CSU_ALL_RW},
 156          {CSU_CSLX_SAI4, CSU_ALL_RW},
 157          {CSU_CSLX_SAI3, CSU_ALL_RW},
 158          {CSU_CSLX_FTM2, CSU_ALL_RW},
 159          {CSU_CSLX_FTM1, CSU_ALL_RW},
 160          {CSU_CSLX_FTM4, CSU_ALL_RW},
 161          {CSU_CSLX_FTM3, CSU_ALL_RW},
 162          {CSU_CSLX_FTM6, CSU_ALL_RW},
 163          {CSU_CSLX_FTM5, CSU_ALL_RW},
 164          {CSU_CSLX_FTM8, CSU_ALL_RW},
 165          {CSU_CSLX_FTM7, CSU_ALL_RW},
 166          {CSU_CSLX_DSCR, CSU_ALL_RW},
 167 };
 168
 169 #endif