arch/arm/include/asm/arch-fsl-layerscape/ns_access.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __FSL_NS_ACCESS_H_
   7 #define __FSL_NS_ACCESS_H_
   8 #include <fsl_csu.h>
   9
  10 enum csu_cslx_ind {
  11         CSU_CSLX_PCIE2_IO = 0,
  12         CSU_CSLX_PCIE1_IO,
  13         CSU_CSLX_MG2TPR_IP,
  14         CSU_CSLX_IFC_MEM,
  15         CSU_CSLX_OCRAM,
  16         CSU_CSLX_GIC,
  17         CSU_CSLX_PCIE1,
  18         CSU_CSLX_OCRAM2,
  19         CSU_CSLX_QSPI_MEM,
  20         CSU_CSLX_PCIE2,
  21         CSU_CSLX_SATA,
  22         CSU_CSLX_USB1,
  23         CSU_CSLX_QM_BM_SWPORTAL,
  24         CSU_CSLX_PCIE3 = 16,
  25         CSU_CSLX_PCIE3_IO,
  26         CSU_CSLX_USB3 = 20,
  27         CSU_CSLX_USB2,
  28         CSU_CSLX_PFE = 23,
  29         CSU_CSLX_SERDES = 32,
  30         CSU_CSLX_QDMA,
  31         CSU_CSLX_LPUART2,
  32         CSU_CSLX_LPUART1,
  33         CSU_CSLX_LPUART4,
  34         CSU_CSLX_LPUART3,
  35         CSU_CSLX_LPUART6,
  36         CSU_CSLX_LPUART5,
  37         CSU_CSLX_DSPI1 = 41,
  38         CSU_CSLX_QSPI,
  39         CSU_CSLX_ESDHC,
  40         CSU_CSLX_IFC = 45,
  41         CSU_CSLX_I2C1,
  42         CSU_CSLX_USB_2,
  43         CSU_CSLX_I2C3 = 48,
  44         CSU_CSLX_I2C2,
  45         CSU_CSLX_DUART2 = 50,
  46         CSU_CSLX_DUART1,
  47         CSU_CSLX_WDT2,
  48         CSU_CSLX_WDT1,
  49         CSU_CSLX_EDMA,
  50         CSU_CSLX_SYS_CNT,
  51         CSU_CSLX_DMA_MUX2,
  52         CSU_CSLX_DMA_MUX1,
  53         CSU_CSLX_DDR,
  54         CSU_CSLX_QUICC,
  55         CSU_CSLX_DCFG_CCU_RCPM = 60,
  56         CSU_CSLX_SECURE_BOOTROM,
  57         CSU_CSLX_SFP,
  58         CSU_CSLX_TMU,
  59         CSU_CSLX_SECURE_MONITOR,
  60         CSU_CSLX_SCFG,
  61         CSU_CSLX_FM = 66,
  62         CSU_CSLX_SEC5_5,
  63         CSU_CSLX_BM,
  64         CSU_CSLX_QM,
  65         CSU_CSLX_GPIO2 = 70,
  66         CSU_CSLX_GPIO1,
  67         CSU_CSLX_GPIO4,
  68         CSU_CSLX_GPIO3,
  69         CSU_CSLX_PLATFORM_CONT,
  70         CSU_CSLX_CSU,
  71         CSU_CSLX_IIC4 = 77,
  72         CSU_CSLX_WDT4,
  73         CSU_CSLX_WDT3,
  74         CSU_CSLX_ESDHC2 = 80,
  75         CSU_CSLX_WDT5 = 81,
  76         CSU_CSLX_SAI2,
  77         CSU_CSLX_SAI1,
  78         CSU_CSLX_SAI4,
  79         CSU_CSLX_SAI3,
  80         CSU_CSLX_FTM2 = 86,
  81         CSU_CSLX_FTM1,
  82         CSU_CSLX_FTM4,
  83         CSU_CSLX_FTM3,
  84         CSU_CSLX_FTM6 = 90,
  85         CSU_CSLX_FTM5,
  86         CSU_CSLX_FTM8,
  87         CSU_CSLX_FTM7,
  88         CSU_CSLX_DSCR = 121,
  89 };
  90
  91 #endif