arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

   1 /*
   2  * LayerScape Internal Memory Map
   3  *
   4  * Copyright 2014 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
  10 #define __ARCH_FSL_LSCH3_IMMAP_H_
  11
  12 #define CONFIG_SYS_IMMR                         0x01000000
  13 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
  14 #define CONFIG_SYS_FSL_DDR2_ADDR                (CONFIG_SYS_IMMR + 0x00090000)
  15 #define CONFIG_SYS_FSL_DDR3_ADDR                0x08210000
  16 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00E00000)
  17 #define CONFIG_SYS_FSL_PMU_ADDR                 (CONFIG_SYS_IMMR + 0x00E30000)
  18 #define CONFIG_SYS_FSL_RST_ADDR                 (CONFIG_SYS_IMMR + 0x00E60000)
  19 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR        (CONFIG_SYS_IMMR + 0x00300000)
  20 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR        (CONFIG_SYS_IMMR + 0x00310000)
  21 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR        (CONFIG_SYS_IMMR + 0x00370000)
  22 #define CONFIG_SYS_FSL_ESDHC_ADDR               (CONFIG_SYS_IMMR + 0x01140000)
  23 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x01240000)
  24 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011C0500)
  25 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011C0600)
  26 #define CONFIG_SYS_FSL_TIMER_ADDR               0x023d0000
  27 #define CONFIG_SYS_FSL_PMU_CLTBENR              (CONFIG_SYS_FSL_PMU_ADDR + \
  28                                                  0x18A0)
  29 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
  30 #define FSL_LSCH3_SVR           (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
  31
  32 #define CONFIG_SYS_FSL_WRIOP1_ADDR              (CONFIG_SYS_IMMR + 0x7B80000)
  33 #define CONFIG_SYS_FSL_WRIOP1_MDIO1     (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
  34 #define CONFIG_SYS_FSL_WRIOP1_MDIO2     (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
  35 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR        (CONFIG_SYS_IMMR + 0xEA0000)
  36
  37 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR            0x70012c000ULL
  38 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR           0x70012d000ULL
  39 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR           0x700132000ULL
  40 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR           0x700133000ULL
  41
  42 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01000000)
  43 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01010000)
  44 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01020000)
  45 #define I2C4_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01030000)
  46
  47 #define CONFIG_SYS_XHCI_USB1_ADDR               (CONFIG_SYS_IMMR + 0x02100000)
  48 #define CONFIG_SYS_XHCI_USB2_ADDR               (CONFIG_SYS_IMMR + 0x02110000)
  49
  50 /* TZ Address Space Controller Definitions */
  51 #define TZASC1_BASE                     0x01100000      /* as per CCSR map. */
  52 #define TZASC2_BASE                     0x01110000      /* as per CCSR map. */
  53 #define TZASC3_BASE                     0x01120000      /* as per CCSR map. */
  54 #define TZASC4_BASE                     0x01130000      /* as per CCSR map. */
  55 #define TZASC_BUILD_CONFIG_REG(x)       ((TZASC1_BASE + (x * 0x10000)))
  56 #define TZASC_ACTION_REG(x)             ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  57 #define TZASC_GATE_KEEPER(x)            ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  58 #define TZASC_REGION_BASE_LOW_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  59 #define TZASC_REGION_BASE_HIGH_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  60 #define TZASC_REGION_TOP_LOW_0(x)       ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  61 #define TZASC_REGION_TOP_HIGH_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  62 #define TZASC_REGION_ATTRIBUTES_0(x)    ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  63 #define TZASC_REGION_ID_ACCESS_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  64
  65 /* SATA */
  66 #define AHCI_BASE_ADDR1                         (CONFIG_SYS_IMMR + 0x02200000)
  67 #define AHCI_BASE_ADDR2                         (CONFIG_SYS_IMMR + 0x02210000)
  68
  69 /* SFP */
  70 #define CONFIG_SYS_SFP_ADDR             (CONFIG_SYS_IMMR + 0x00e80200)
  71
  72 /* SEC */
  73 #define CONFIG_SYS_FSL_SEC_OFFSET               0x07000000ull
  74 #define CONFIG_SYS_FSL_JR0_OFFSET               0x07010000ull
  75 #define CONFIG_SYS_FSL_SEC_ADDR \
  76         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
  77 #define CONFIG_SYS_FSL_JR0_ADDR \
  78         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
  79
  80 /* Security Monitor */
  81 #define CONFIG_SYS_SEC_MON_ADDR         (CONFIG_SYS_IMMR + 0x00e90000)
  82
  83 /* MMU 500 */
  84 #define SMMU_SCR0                       (SMMU_BASE + 0x0)
  85 #define SMMU_SCR1                       (SMMU_BASE + 0x4)
  86 #define SMMU_SCR2                       (SMMU_BASE + 0x8)
  87 #define SMMU_SACR                       (SMMU_BASE + 0x10)
  88 #define SMMU_IDR0                       (SMMU_BASE + 0x20)
  89 #define SMMU_IDR1                       (SMMU_BASE + 0x24)
  90
  91 #define SMMU_NSCR0                      (SMMU_BASE + 0x400)
  92 #define SMMU_NSCR2                      (SMMU_BASE + 0x408)
  93 #define SMMU_NSACR                      (SMMU_BASE + 0x410)
  94
  95 #define SCR0_CLIENTPD_MASK              0x00000001
  96 #define SCR0_USFCFG_MASK                0x00000400
  97
  98
  99 /* PCIe */
 100 #define CONFIG_SYS_PCIE1_ADDR                   (CONFIG_SYS_IMMR + 0x2400000)
 101 #define CONFIG_SYS_PCIE2_ADDR                   (CONFIG_SYS_IMMR + 0x2500000)
 102 #define CONFIG_SYS_PCIE3_ADDR                   (CONFIG_SYS_IMMR + 0x2600000)
 103 #define CONFIG_SYS_PCIE4_ADDR                   (CONFIG_SYS_IMMR + 0x2700000)
 104 #define CONFIG_SYS_PCIE1_PHYS_ADDR              0x1000000000ULL
 105 #define CONFIG_SYS_PCIE2_PHYS_ADDR              0x1200000000ULL
 106 #define CONFIG_SYS_PCIE3_PHYS_ADDR              0x1400000000ULL
 107 #define CONFIG_SYS_PCIE4_PHYS_ADDR              0x1600000000ULL
 108 /* LUT registers */
 109 #define PCIE_LUT_BASE                           0x80000
 110 #define PCIE_LUT_LCTRL0                         0x7F8
 111 #define PCIE_LUT_DBG                            0x7FC
 112 #define PCIE_LUT_UDR(n)         (0x800 + (n) * 8)
 113 #define PCIE_LUT_LDR(n)         (0x804 + (n) * 8)
 114 #define PCIE_LUT_ENABLE         (1 << 31)
 115 #define PCIE_LUT_ENTRY_COUNT    32
 116
 117 /* Device Configuration */
 118 #define DCFG_BASE               0x01e00000
 119 #define DCFG_PORSR1                     0x000
 120 #define DCFG_PORSR1_RCW_SRC             0xff800000
 121 #define DCFG_PORSR1_RCW_SRC_NOR         0x12f00000
 122 #define DCFG_RCWSR13                    0x130
 123 #define DCFG_RCWSR13_DSPI               (0 << 8)
 124 #define DCFG_RCWSR15                    0x138
 125 #define DCFG_RCWSR15_IFCGRPABASE_QSPI   0x3
 126
 127 #define DCFG_DCSR_BASE          0X700100000ULL
 128 #define DCFG_DCSR_PORCR1                0x000
 129
 130 /* Interrupt Sampling Control */
 131 #define ISC_BASE                0x01F70000
 132 #define IRQCR_OFFSET            0x14
 133
 134 /* Supplemental Configuration */
 135 #define SCFG_BASE               0x01fc0000
 136 #define SCFG_USB3PRM1CR                 0x000
 137 #define SCFG_USB3PRM1CR_INIT            0x27672b2a
 138 #define SCFG_QSPICLKCTLR        0x10
 139
 140 #define TP_ITYP_AV              0x00000001      /* Initiator available */
 141 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
 142 #define TP_ITYP_TYPE_ARM        0x0
 143 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
 144 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
 145 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
 146 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
 147 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
 148 #define TY_ITYP_VER_A7          0x1
 149 #define TY_ITYP_VER_A53         0x2
 150 #define TY_ITYP_VER_A57         0x3
 151 #define TY_ITYP_VER_A72         0x4
 152
 153 #define TP_CLUSTER_EOC          0x80000000      /* end of clusters */
 154 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 155 #define TP_INIT_PER_CLUSTER     4
 156 /* This is chassis generation 3 */
 157 #ifndef __ASSEMBLY__
 158 struct sys_info {
 159         unsigned long freq_processor[CONFIG_MAX_CPUS];
 160         unsigned long freq_systembus;
 161         unsigned long freq_ddrbus;
 162 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 163         unsigned long freq_ddrbus2;
 164 #endif
 165         unsigned long freq_localbus;
 166         unsigned long freq_qe;
 167 #ifdef CONFIG_SYS_DPAA_FMAN
 168         unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
 169 #endif
 170 #ifdef CONFIG_SYS_DPAA_QBMAN
 171         unsigned long freq_qman;
 172 #endif
 173 #ifdef CONFIG_SYS_DPAA_PME
 174         unsigned long freq_pme;
 175 #endif
 176 };
 177
 178 /* Global Utilities Block */
 179 struct ccsr_gur {
 180         u32     porsr1;         /* POR status 1 */
 181         u32     porsr2;         /* POR status 2 */
 182         u8      res_008[0x20-0x8];
 183         u32     gpporcr1;       /* General-purpose POR configuration */
 184         u32     gpporcr2;       /* General-purpose POR configuration 2 */
 185 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT      25
 186 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK       0x1F
 187 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT   20
 188 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK    0x1F
 189         u32     dcfg_fusesr;    /* Fuse status register */
 190         u32     gpporcr3;
 191         u32     gpporcr4;
 192         u8      res_034[0x70-0x34];
 193         u32     devdisr;        /* Device disable control */
 194         u32     devdisr2;       /* Device disable control 2 */
 195         u32     devdisr3;       /* Device disable control 3 */
 196         u32     devdisr4;       /* Device disable control 4 */
 197         u32     devdisr5;       /* Device disable control 5 */
 198         u32     devdisr6;       /* Device disable control 6 */
 199         u32     devdisr7;       /* Device disable control 7 */
 200 #define FSL_CHASSIS3_DEVDISR2_DPMAC1    0x00000001
 201 #define FSL_CHASSIS3_DEVDISR2_DPMAC2    0x00000002
 202 #define FSL_CHASSIS3_DEVDISR2_DPMAC3    0x00000004
 203 #define FSL_CHASSIS3_DEVDISR2_DPMAC4    0x00000008
 204 #define FSL_CHASSIS3_DEVDISR2_DPMAC5    0x00000010
 205 #define FSL_CHASSIS3_DEVDISR2_DPMAC6    0x00000020
 206 #define FSL_CHASSIS3_DEVDISR2_DPMAC7    0x00000040
 207 #define FSL_CHASSIS3_DEVDISR2_DPMAC8    0x00000080
 208 #define FSL_CHASSIS3_DEVDISR2_DPMAC9    0x00000100
 209 #define FSL_CHASSIS3_DEVDISR2_DPMAC10   0x00000200
 210 #define FSL_CHASSIS3_DEVDISR2_DPMAC11   0x00000400
 211 #define FSL_CHASSIS3_DEVDISR2_DPMAC12   0x00000800
 212 #define FSL_CHASSIS3_DEVDISR2_DPMAC13   0x00001000
 213 #define FSL_CHASSIS3_DEVDISR2_DPMAC14   0x00002000
 214 #define FSL_CHASSIS3_DEVDISR2_DPMAC15   0x00004000
 215 #define FSL_CHASSIS3_DEVDISR2_DPMAC16   0x00008000
 216 #define FSL_CHASSIS3_DEVDISR2_DPMAC17   0x00010000
 217 #define FSL_CHASSIS3_DEVDISR2_DPMAC18   0x00020000
 218 #define FSL_CHASSIS3_DEVDISR2_DPMAC19   0x00040000
 219 #define FSL_CHASSIS3_DEVDISR2_DPMAC20   0x00080000
 220 #define FSL_CHASSIS3_DEVDISR2_DPMAC21   0x00100000
 221 #define FSL_CHASSIS3_DEVDISR2_DPMAC22   0x00200000
 222 #define FSL_CHASSIS3_DEVDISR2_DPMAC23   0x00400000
 223 #define FSL_CHASSIS3_DEVDISR2_DPMAC24   0x00800000
 224         u8      res_08c[0x90-0x8c];
 225         u32     coredisru;      /* uppper portion for support of 64 cores */
 226         u32     coredisrl;      /* lower portion for support of 64 cores */
 227         u8      res_098[0xa0-0x98];
 228         u32     pvr;            /* Processor version */
 229         u32     svr;            /* System version */
 230         u32     mvr;            /* Manufacturing version */
 231         u8      res_0ac[0x100-0xac];
 232         u32     rcwsr[32];      /* Reset control word status */
 233
 234 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT   2
 235 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK    0x1f
 236 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT   10
 237 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK    0x3f
 238 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT  18
 239 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK   0x3f
 240 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x00FF0000
 241 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
 242 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
 243 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
 244 #define RCW_SB_EN_REG_INDEX     9
 245 #define RCW_SB_EN_MASK          0x00000400
 246
 247         u8      res_180[0x200-0x180];
 248         u32     scratchrw[32];  /* Scratch Read/Write */
 249         u8      res_280[0x300-0x280];
 250         u32     scratchw1r[4];  /* Scratch Read (Write once) */
 251         u8      res_310[0x400-0x310];
 252         u32     bootlocptrl;    /* Boot location pointer low-order addr */
 253         u32     bootlocptrh;    /* Boot location pointer high-order addr */
 254         u8      res_408[0x500-0x408];
 255         u8      res_500[0x740-0x500];   /* add more registers when needed */
 256         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 257         struct {
 258                 u32     upper;
 259                 u32     lower;
 260         } tp_cluster[3];        /* Core Cluster n Topology Register */
 261         u8      res_858[0x1000-0x858];
 262 };
 263
 264
 265 struct ccsr_clk_cluster_group {
 266         struct {
 267                 u8      res_00[0x10];
 268                 u32     csr;
 269                 u8      res_14[0x20-0x14];
 270         } hwncsr[3];
 271         u8      res_60[0x80-0x60];
 272         struct {
 273                 u32     gsr;
 274                 u8      res_84[0xa0-0x84];
 275         } pllngsr[3];
 276         u8      res_e0[0x100-0xe0];
 277 };
 278
 279 struct ccsr_clk_ctrl {
 280         struct {
 281                 u32 csr;        /* core cluster n clock control status */
 282                 u8  res_04[0x20-0x04];
 283         } clkcncsr[8];
 284 };
 285
 286 struct ccsr_reset {
 287         u32 rstcr;                      /* 0x000 */
 288         u32 rstcrsp;                    /* 0x004 */
 289         u8 res_008[0x10-0x08];          /* 0x008 */
 290         u32 rstrqmr1;                   /* 0x010 */
 291         u32 rstrqmr2;                   /* 0x014 */
 292         u32 rstrqsr1;                   /* 0x018 */
 293         u32 rstrqsr2;                   /* 0x01c */
 294         u32 rstrqwdtmrl;                /* 0x020 */
 295         u32 rstrqwdtmru;                /* 0x024 */
 296         u8 res_028[0x30-0x28];          /* 0x028 */
 297         u32 rstrqwdtsrl;                /* 0x030 */
 298         u32 rstrqwdtsru;                /* 0x034 */
 299         u8 res_038[0x60-0x38];          /* 0x038 */
 300         u32 brrl;                       /* 0x060 */
 301         u32 brru;                       /* 0x064 */
 302         u8 res_068[0x80-0x68];          /* 0x068 */
 303         u32 pirset;                     /* 0x080 */
 304         u32 pirclr;                     /* 0x084 */
 305         u8 res_088[0x90-0x88];          /* 0x088 */
 306         u32 brcorenbr;                  /* 0x090 */
 307         u8 res_094[0x100-0x94];         /* 0x094 */
 308         u32 rcw_reqr;                   /* 0x100 */
 309         u32 rcw_completion;             /* 0x104 */
 310         u8 res_108[0x110-0x108];        /* 0x108 */
 311         u32 pbi_reqr;                   /* 0x110 */
 312         u32 pbi_completion;             /* 0x114 */
 313         u8 res_118[0xa00-0x118];        /* 0x118 */
 314         u32 qmbm_warmrst;               /* 0xa00 */
 315         u32 soc_warmrst;                /* 0xa04 */
 316         u8 res_a08[0xbf8-0xa08];        /* 0xa08 */
 317         u32 ip_rev1;                    /* 0xbf8 */
 318         u32 ip_rev2;                    /* 0xbfc */
 319 };
 320
 321 #endif /*__ASSEMBLY__*/
 322 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */