2 * Copyright 2013-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__
8 #define __ARCH_FSL_LSCH2_IMMAP_H__
10 #include <fsl_immap.h>
12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_DCSRBAR 0x20000000
14 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
18 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
19 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
20 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
21 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
22 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
23 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
24 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
25 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
26 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
27 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
28 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
29 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
30 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
31 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
32 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
33 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
34 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
35 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
36 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
37 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
38 #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
39 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
40 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
41 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
42 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
43 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
45 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
47 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
48 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
49 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
50 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
52 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
54 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
55 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
57 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
59 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
61 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
62 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
63 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
65 #ifdef CONFIG_ARCH_LS1012A
66 #define PCIE_LUT_BASE 0xC0000
68 #define PCIE_LUT_BASE 0x10000
70 #define PCIE_LUT_LCTRL0 0x7F8
71 #define PCIE_LUT_DBG 0x7FC
73 /* TZ Address Space Controller Definitions */
74 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
75 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
76 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
77 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
78 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
79 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
80 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
81 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
82 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
83 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
84 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
85 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
86 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
88 #define TP_ITYP_AV 0x00000001 /* Initiator available */
89 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
90 #define TP_ITYP_TYPE_ARM 0x0
91 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
92 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
93 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
94 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
95 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
96 #define TY_ITYP_VER_A7 0x1
97 #define TY_ITYP_VER_A53 0x2
98 #define TY_ITYP_VER_A57 0x3
99 #define TY_ITYP_VER_A72 0x4
101 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
102 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
103 #define TP_INIT_PER_CLUSTER 4
106 * Define default values for some CCSR macros to make header files cleaner*
108 * To completely disable CCSR relocation in a board header file, define
109 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
110 * to a value that is the same as CONFIG_SYS_CCSRBAR.
113 #ifdef CONFIG_SYS_CCSRBAR_PHYS
114 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
115 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
118 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
119 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
120 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
121 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
124 #ifndef CONFIG_SYS_CCSRBAR
125 #define CONFIG_SYS_CCSRBAR 0x01000000
128 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
129 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
132 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
133 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
136 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
137 CONFIG_SYS_CCSRBAR_PHYS_LOW)
140 unsigned long freq_processor[CONFIG_MAX_CPUS];
141 /* frequency of platform PLL */
142 unsigned long freq_systembus;
143 unsigned long freq_ddrbus;
144 unsigned long freq_localbus;
145 unsigned long freq_sdhc;
146 #ifdef CONFIG_SYS_DPAA_FMAN
147 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
149 unsigned long freq_qman;
152 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
153 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
154 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
155 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
156 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
157 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
158 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
160 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
161 #define CONFIG_SYS_FSL_FM1_ADDR \
162 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
163 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
164 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
166 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
167 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
168 #define CONFIG_SYS_FSL_SEC_ADDR \
169 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
170 #define CONFIG_SYS_FSL_JR0_ADDR \
171 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
173 /* Device Configuration and Pin Control */
174 #define DCFG_DCSR_PORCR1 0x0
177 u32 porsr1; /* POR status 1 */
178 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
179 u32 porsr2; /* POR status 2 */
180 u8 res_008[0x20-0x8];
181 u32 gpporcr1; /* General-purpose POR configuration */
183 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25
184 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
185 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20
186 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
187 u32 dcfg_fusesr; /* Fuse status register */
188 u8 res_02c[0x70-0x2c];
189 u32 devdisr; /* Device disable control */
190 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
191 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
192 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
193 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
194 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
195 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
196 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
197 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
198 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
199 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
200 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
201 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
202 u32 devdisr2; /* Device disable control 2 */
203 u32 devdisr3; /* Device disable control 3 */
204 u32 devdisr4; /* Device disable control 4 */
205 u32 devdisr5; /* Device disable control 5 */
206 u32 devdisr6; /* Device disable control 6 */
207 u32 devdisr7; /* Device disable control 7 */
208 u8 res_08c[0x94-0x8c];
209 u32 coredisru; /* uppper portion for support of 64 cores */
210 u32 coredisrl; /* lower portion for support of 64 cores */
211 u8 res_09c[0xa0-0x9c];
212 u32 pvr; /* Processor version */
213 u32 svr; /* System version */
214 u32 mvr; /* Manufacturing version */
215 u8 res_0ac[0xb0-0xac];
216 u32 rstcr; /* Reset control */
217 u32 rstrqpblsr; /* Reset request preboot loader status */
218 u8 res_0b8[0xc0-0xb8];
219 u32 rstrqmr1; /* Reset request mask */
220 u8 res_0c4[0xc8-0xc4];
221 u32 rstrqsr1; /* Reset request status */
222 u8 res_0cc[0xd4-0xcc];
223 u32 rstrqwdtmrl; /* Reset request WDT mask */
224 u8 res_0d8[0xdc-0xd8];
225 u32 rstrqwdtsrl; /* Reset request WDT status */
226 u8 res_0e0[0xe4-0xe0];
227 u32 brrl; /* Boot release */
228 u8 res_0e8[0x100-0xe8];
229 u32 rcwsr[16]; /* Reset control word status */
230 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
231 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
232 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
233 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
234 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
235 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
236 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
237 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
238 #define RCW_SB_EN_REG_INDEX 7
239 #define RCW_SB_EN_MASK 0x00200000
241 u8 res_140[0x200-0x140];
242 u32 scratchrw[4]; /* Scratch Read/Write */
243 u8 res_210[0x300-0x210];
244 u32 scratchw1r[4]; /* Scratch Read (Write once) */
245 u8 res_310[0x400-0x310];
247 u8 res_430[0x500-0x430];
249 /* PCI Express n Logical I/O Device Number register */
250 u32 dcfg_ccsr_pex1liodnr;
251 u32 dcfg_ccsr_pex2liodnr;
252 u32 dcfg_ccsr_pex3liodnr;
253 u32 dcfg_ccsr_pex4liodnr;
254 /* RIO n Logical I/O Device Number register */
255 u32 dcfg_ccsr_rio1liodnr;
256 u32 dcfg_ccsr_rio2liodnr;
257 u32 dcfg_ccsr_rio3liodnr;
258 u32 dcfg_ccsr_rio4liodnr;
259 /* USB Logical I/O Device Number register */
260 u32 dcfg_ccsr_usb1liodnr;
261 u32 dcfg_ccsr_usb2liodnr;
262 u32 dcfg_ccsr_usb3liodnr;
263 u32 dcfg_ccsr_usb4liodnr;
264 /* SD/MMC Logical I/O Device Number register */
265 u32 dcfg_ccsr_sdmmc1liodnr;
266 u32 dcfg_ccsr_sdmmc2liodnr;
267 u32 dcfg_ccsr_sdmmc3liodnr;
268 u32 dcfg_ccsr_sdmmc4liodnr;
269 /* RIO Message Unit Logical I/O Device Number register */
270 u32 dcfg_ccsr_riomaintliodnr;
272 u8 res_544[0x550-0x544];
274 u8 res_560[0x570-0x560];
276 u32 dcfg_ccsr_misc1liodnr;
277 u32 dcfg_ccsr_misc2liodnr;
278 u32 dcfg_ccsr_misc3liodnr;
279 u32 dcfg_ccsr_misc4liodnr;
280 u32 dcfg_ccsr_dma1liodnr;
281 u32 dcfg_ccsr_dma2liodnr;
282 u32 dcfg_ccsr_dma3liodnr;
283 u32 dcfg_ccsr_dma4liodnr;
284 u32 dcfg_ccsr_spare1liodnr;
285 u32 dcfg_ccsr_spare2liodnr;
286 u32 dcfg_ccsr_spare3liodnr;
287 u32 dcfg_ccsr_spare4liodnr;
288 u8 res_5a0[0x600-0x5a0];
294 u8 res_60c[0x610-0x60c];
295 u32 dcfg_ccsr_gensr1;
296 u32 dcfg_ccsr_gensr2;
297 u32 dcfg_ccsr_gensr3;
298 u32 dcfg_ccsr_gensr4;
299 u32 dcfg_ccsr_gencr1;
300 u32 dcfg_ccsr_gencr2;
301 u32 dcfg_ccsr_gencr3;
302 u32 dcfg_ccsr_gencr4;
303 u32 dcfg_ccsr_gencr5;
304 u32 dcfg_ccsr_gencr6;
305 u32 dcfg_ccsr_gencr7;
306 u8 res_63c[0x658-0x63c];
307 u32 dcfg_ccsr_cgensr1;
308 u32 dcfg_ccsr_cgensr0;
309 u8 res_660[0x678-0x660];
310 u32 dcfg_ccsr_cgencr1;
312 u32 dcfg_ccsr_cgencr0;
313 u8 res_680[0x700-0x680];
314 u32 dcfg_ccsr_sriopstecr;
315 u32 dcfg_ccsr_dcsrcr;
317 u8 res_708[0x740-0x708]; /* add more registers when needed */
318 u32 tp_ityp[64]; /* Topology Initiator Type Register */
323 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
324 u32 dcfg_ccsr_qmbm_warmrst;
325 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
326 u32 dcfg_ccsr_reserved0;
327 u32 dcfg_ccsr_reserved1;
330 #define SCFG_QSPI_CLKSEL 0x40100000
331 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
332 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
333 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
334 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000
335 #define SCFG_USBPWRFAULT_SHARED 0x00000001
336 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002
337 #define SCFG_USBPWRFAULT_USB3_SHIFT 4
338 #define SCFG_USBPWRFAULT_USB2_SHIFT 2
339 #define SCFG_USBPWRFAULT_USB1_SHIFT 0
341 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
342 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
343 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
344 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
346 /* Supplemental Configuration Unit */
348 u8 res_000[0x100-0x000];
351 u8 res_108[0x114-0x108];
360 u8 res_140[0x158-0x140];
363 u8 res_160[0x180-0x160];
365 u8 res_184[0x188-0x184];
368 u8 res_190[0x1a4-0x190];
370 u8 res_1a8[0x1ac-0x1a8];
372 u8 res_1b0[0x204-0x1b0];
374 u8 res_208[0x220-0x208];
384 u8 res_244[0x400-0x244];
389 u32 usbdrvvbus_selcr;
390 u32 usbpwrfault_selcr;
391 u32 usb_refclk_selcr1;
392 u32 usb_refclk_selcr2;
393 u32 usb_refclk_selcr3;
394 u8 res_424[0x600-0x424];
396 u8 res_610[0x680-0x610];
398 u8 res_684[0x1000-0x684];
401 u8 res_1008[0x2000-0x1008];
404 u8 res_2008[0x3000-0x2008];
412 u32 clkcncsr; /* core cluster n clock control status */
414 u32 clkcghwacsr; /* Clock generator n hardware accelerator */
417 u8 res_040[0x780]; /* 0x100 */
423 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
425 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
427 u32 plldgsr; /* 0xc20 DDR PLL General Status */
444 #define SRDS_MAX_LANES 4
447 u32 rstctl; /* Reset Control Register */
448 #define SRDS_RSTCTL_RST 0x80000000
449 #define SRDS_RSTCTL_RSTDONE 0x40000000
450 #define SRDS_RSTCTL_RSTERR 0x20000000
451 #define SRDS_RSTCTL_SWRST 0x10000000
452 #define SRDS_RSTCTL_SDEN 0x00000020
453 #define SRDS_RSTCTL_SDRST_B 0x00000040
454 #define SRDS_RSTCTL_PLLRST_B 0x00000080
455 u32 pllcr0; /* PLL Control Register 0 */
456 #define SRDS_PLLCR0_POFF 0x80000000
457 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
458 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
459 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
460 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
461 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
462 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
463 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
464 #define SRDS_PLLCR0_PLL_LCK 0x00800000
465 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
466 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
467 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
468 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
469 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
470 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
471 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
472 u32 pllcr1; /* PLL Control Register 1 */
473 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
474 u32 res_0c; /* 0x00c */
477 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
478 u8 res_1c[0x20-0x1c];
480 u8 res_40[0x90-0x40];
481 u32 srdstcalcr; /* 0x90 TX Calibration Control */
482 u8 res_94[0xa0-0x94];
483 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
484 u8 res_a4[0xb0-0xa4];
485 u32 srdsgr0; /* 0xb0 General Register 0 */
486 u8 res_b4[0x100-0xb4];
488 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */
489 u8 res_104[0x120-0x104];
490 } lnpssr[4]; /* Lane A, B, C, D */
491 u8 res_180[0x200-0x180];
492 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */
493 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */
494 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */
495 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */
496 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */
497 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */
498 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */
499 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */
500 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */
501 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */
502 u32 srdspccra; /* 0x228 Protocol Configuration A */
503 u32 srdspccrb; /* 0x22c Protocol Configuration B */
504 u8 res_230[0x800-0x230];
506 u32 gcr0; /* 0x800 General Control Register 0 */
507 u32 gcr1; /* 0x804 General Control Register 1 */
508 u32 gcr2; /* 0x808 General Control Register 2 */
510 u32 recr0; /* 0x810 Receive Equalization Control */
512 u32 tecr0; /* 0x818 Transmit Equalization Control */
514 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
515 u8 res_824[0x83c-0x824];
517 } lane[4]; /* Lane A, B, C, D */
518 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */
520 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
521 u8 res_1004[0x1040-0x1004];
523 u8 res_10c0[0x1800-0x10c0];
525 u8 res_1800[0x1804-0x1800];
526 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */
527 u8 res_1808[0x180c-0x1808];
528 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */
529 } sgmii[4]; /* Lane A, B, C, D */
530 u8 res_1840[0x1880-0x1840];
532 u8 res_1880[0x1884-0x1880];
533 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */
534 u8 res_1888[0x188c-0x1888];
535 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */
536 } qsgmii[2]; /* Lane A, B */
537 u8 res_18a0[0x1980-0x18a0];
539 u8 res_1980[0x1984-0x1980];
540 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
541 u8 res_1988[0x198c-0x1988];
542 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
543 } xfi[2]; /* Lane A, B */
544 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
547 #define CCI400_CTRLORD_TERM_BARRIER 0x00000008
548 #define CCI400_CTRLORD_EN_BARRIER 0
549 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002
550 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
551 #define CCI400_SNOOP_REQ_EN 0x00000001
553 /* CCI-400 registers */
555 u32 ctrl_ord; /* Control Override */
556 u32 spec_ctrl; /* Speculation Control */
557 u32 secure_access; /* Secure Access */
558 u32 status; /* Status */
559 u32 impr_err; /* Imprecise Error */
560 u8 res_14[0x100 - 0x14];
561 u32 pmcr; /* Performance Monitor Control */
562 u8 res_104[0xfd0 - 0x104];
563 u32 pid[8]; /* Peripheral ID */
564 u32 cid[4]; /* Component ID */
566 u32 snoop_ctrl; /* Snoop Control */
567 u32 sha_ord; /* Shareable Override */
568 u8 res_1008[0x1100 - 0x1008];
569 u32 rc_qos_ord; /* read channel QoS Value Override */
570 u32 wc_qos_ord; /* read channel QoS Value Override */
571 u8 res_1108[0x110c - 0x1108];
572 u32 qos_ctrl; /* QoS Control */
573 u32 max_ot; /* Max OT */
574 u8 res_1114[0x1130 - 0x1114];
575 u32 target_lat; /* Target Latency */
576 u32 latency_regu; /* Latency Regulation */
577 u32 qos_range; /* QoS Range */
578 u8 res_113c[0x2000 - 0x113c];
579 } slave[5]; /* Slave Interface */
580 u8 res_6000[0x9004 - 0x6000];
581 u32 cycle_counter; /* Cycle counter */
582 u32 count_ctrl; /* Count Control */
583 u32 overflow_status; /* Overflow Flag Status */
584 u8 res_9010[0xa000 - 0x9010];
586 u32 event_select; /* Event Select */
587 u32 event_count; /* Event Count */
588 u32 counter_ctrl; /* Counter Control */
589 u32 overflow_status; /* Overflow Flag Status */
590 u8 res_a010[0xb000 - 0xa010];
591 } pcounter[4]; /* Performance Counter */
592 u8 res_e004[0x10000 - 0xe004];
596 #define SMMU_SCR0 (SMMU_BASE + 0x0)
597 #define SMMU_SCR1 (SMMU_BASE + 0x4)
598 #define SMMU_SCR2 (SMMU_BASE + 0x8)
599 #define SMMU_SACR (SMMU_BASE + 0x10)
600 #define SMMU_IDR0 (SMMU_BASE + 0x20)
601 #define SMMU_IDR1 (SMMU_BASE + 0x24)
603 #define SMMU_NSCR0 (SMMU_BASE + 0x400)
604 #define SMMU_NSCR2 (SMMU_BASE + 0x408)
605 #define SMMU_NSACR (SMMU_BASE + 0x410)
607 #define SCR0_CLIENTPD_MASK 0x00000001
608 #define SCR0_USFCFG_MASK 0x00000400
612 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/