Merge branch 'master' of git://git.denx.de/u-boot
[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / cpu.h
1 /*
2  * Copyright 2014-2015, Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef _FSL_LAYERSCAPE_CPU_H
8 #define _FSL_LAYERSCAPE_CPU_H
9
10 static struct cpu_type cpu_type_list[] = {
11         CPU_TYPE_ENTRY(LS2080, LS2080, 8),
12         CPU_TYPE_ENTRY(LS2085, LS2085, 8),
13         CPU_TYPE_ENTRY(LS2045, LS2045, 4),
14         CPU_TYPE_ENTRY(LS1043, LS1043, 4),
15         CPU_TYPE_ENTRY(LS1023, LS1023, 2),
16         CPU_TYPE_ENTRY(LS2040, LS2040, 4),
17         CPU_TYPE_ENTRY(LS1012, LS1012, 1),
18 };
19
20 #ifndef CONFIG_SYS_DCACHE_OFF
21
22 #define SECTION_SHIFT_L0                39UL
23 #define SECTION_SHIFT_L1                30UL
24 #define SECTION_SHIFT_L2                21UL
25 #define BLOCK_SIZE_L0                   0x8000000000
26 #define BLOCK_SIZE_L1                   0x40000000
27 #define BLOCK_SIZE_L2                   0x200000
28 #define NUM_OF_ENTRY                    512
29 #define TCR_EL2_PS_40BIT                (2 << 16)
30
31 #define LAYERSCAPE_VA_BITS              (40)
32 #define LAYERSCAPE_TCR          (TCR_TG0_4K             | \
33                                 TCR_EL2_PS_40BIT        | \
34                                 TCR_SHARED_NON          | \
35                                 TCR_ORGN_NC             | \
36                                 TCR_IRGN_NC             | \
37                                 TCR_T0SZ(LAYERSCAPE_VA_BITS))
38 #define LAYERSCAPE_TCR_FINAL    (TCR_TG0_4K             | \
39                                 TCR_EL2_PS_40BIT        | \
40                                 TCR_SHARED_OUTER        | \
41                                 TCR_ORGN_WBWA           | \
42                                 TCR_IRGN_WBWA           | \
43                                 TCR_T0SZ(LAYERSCAPE_VA_BITS))
44
45 #ifdef CONFIG_FSL_LSCH3
46 #define CONFIG_SYS_FSL_CCSR_BASE        0x00000000
47 #define CONFIG_SYS_FSL_CCSR_SIZE        0x10000000
48 #define CONFIG_SYS_FSL_QSPI_BASE1       0x20000000
49 #define CONFIG_SYS_FSL_QSPI_SIZE1       0x10000000
50 #define CONFIG_SYS_FSL_IFC_BASE1        0x30000000
51 #define CONFIG_SYS_FSL_IFC_SIZE1        0x10000000
52 #define CONFIG_SYS_FSL_IFC_SIZE1_1      0x400000
53 #define CONFIG_SYS_FSL_DRAM_BASE1       0x80000000
54 #define CONFIG_SYS_FSL_DRAM_SIZE1       0x80000000
55 #define CONFIG_SYS_FSL_QSPI_BASE2       0x400000000
56 #define CONFIG_SYS_FSL_QSPI_SIZE2       0x100000000
57 #define CONFIG_SYS_FSL_IFC_BASE2        0x500000000
58 #define CONFIG_SYS_FSL_IFC_SIZE2        0x100000000
59 #define CONFIG_SYS_FSL_DCSR_BASE        0x700000000
60 #define CONFIG_SYS_FSL_DCSR_SIZE        0x40000000
61 #define CONFIG_SYS_FSL_MC_BASE          0x80c000000
62 #define CONFIG_SYS_FSL_MC_SIZE          0x4000000
63 #define CONFIG_SYS_FSL_NI_BASE          0x810000000
64 #define CONFIG_SYS_FSL_NI_SIZE          0x8000000
65 #define CONFIG_SYS_FSL_QBMAN_BASE       0x818000000
66 #define CONFIG_SYS_FSL_QBMAN_SIZE       0x8000000
67 #define CONFIG_SYS_FSL_QBMAN_SIZE_1     0x4000000
68 #define CONFIG_SYS_PCIE1_PHYS_SIZE      0x200000000
69 #define CONFIG_SYS_PCIE2_PHYS_SIZE      0x200000000
70 #define CONFIG_SYS_PCIE3_PHYS_SIZE      0x200000000
71 #define CONFIG_SYS_PCIE4_PHYS_SIZE      0x200000000
72 #define CONFIG_SYS_FSL_WRIOP1_BASE      0x4300000000
73 #define CONFIG_SYS_FSL_WRIOP1_SIZE      0x100000000
74 #define CONFIG_SYS_FSL_AIOP1_BASE       0x4b00000000
75 #define CONFIG_SYS_FSL_AIOP1_SIZE       0x100000000
76 #define CONFIG_SYS_FSL_PEBUF_BASE       0x4c00000000
77 #define CONFIG_SYS_FSL_PEBUF_SIZE       0x400000000
78 #define CONFIG_SYS_FSL_DRAM_BASE2       0x8080000000
79 #define CONFIG_SYS_FSL_DRAM_SIZE2       0x7F80000000
80 #elif defined(CONFIG_FSL_LSCH2)
81 #define CONFIG_SYS_FSL_BOOTROM_BASE     0x0
82 #define CONFIG_SYS_FSL_BOOTROM_SIZE     0x1000000
83 #define CONFIG_SYS_FSL_CCSR_BASE        0x1000000
84 #define CONFIG_SYS_FSL_CCSR_SIZE        0xf000000
85 #define CONFIG_SYS_FSL_DCSR_BASE        0x20000000
86 #define CONFIG_SYS_FSL_DCSR_SIZE        0x4000000
87 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
88 #define CONFIG_SYS_FSL_QSPI_SIZE        0x20000000
89 #define CONFIG_SYS_FSL_IFC_BASE         0x60000000
90 #define CONFIG_SYS_FSL_IFC_SIZE         0x20000000
91 #define CONFIG_SYS_FSL_DRAM_BASE1       0x80000000
92 #define CONFIG_SYS_FSL_DRAM_SIZE1       0x80000000
93 #define CONFIG_SYS_FSL_QBMAN_BASE       0x500000000
94 #define CONFIG_SYS_FSL_QBMAN_SIZE       0x10000000
95 #define CONFIG_SYS_FSL_DRAM_BASE2       0x880000000
96 #define CONFIG_SYS_FSL_DRAM_SIZE2       0x780000000     /* 30GB */
97 #define CONFIG_SYS_PCIE1_PHYS_SIZE      0x800000000
98 #define CONFIG_SYS_PCIE2_PHYS_SIZE      0x800000000
99 #define CONFIG_SYS_PCIE3_PHYS_SIZE      0x800000000
100 #define CONFIG_SYS_FSL_DRAM_BASE3       0x8800000000
101 #define CONFIG_SYS_FSL_DRAM_SIZE3       0x7800000000    /* 480GB */
102 #endif
103
104 struct sys_mmu_table {
105         u64 virt_addr;
106         u64 phys_addr;
107         u64 size;
108         u64 memory_type;
109         u64 attribute;
110 };
111
112 struct table_info {
113         u64 *ptr;
114         u64 table_base;
115         u64 entry_size;
116 };
117
118 static const struct sys_mmu_table early_mmu_table[] = {
119 #ifdef CONFIG_FSL_LSCH3
120         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
121           CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
122           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
123         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
124           CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
125         /* For IFC Region #1, only the first 4MB is cache-enabled */
126         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
127           CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
128         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
129           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
130           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
131           MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
132         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
133           CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
134         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
135           CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
136           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
137         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
138         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
139           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
140           MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
141         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
142           CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
143           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
144         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
145           CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
146           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
147 #elif defined(CONFIG_FSL_LSCH2)
148         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
149           CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
150           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
151         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
152           CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
153         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
154           CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
155           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
156         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
157           CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
158         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
159           CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
160         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
161           CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
162           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
163         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
164           CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
165           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
166 #endif
167 };
168
169 static const struct sys_mmu_table final_mmu_table[] = {
170 #ifdef CONFIG_FSL_LSCH3
171         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
172           CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
173           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
174         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
175           CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
176         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
177           CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
178           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
179         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
180           CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
181           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
182         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
183           CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
184         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
185           CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
186           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
187         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
188           CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
189           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
190         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
191           CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
192           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
193         /* For QBMAN portal, only the first 64MB is cache-enabled */
194         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
195           CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
196           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS },
197         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
198           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
199           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
200           MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
201         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
202           CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
203           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
204         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
205           CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
206           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
207         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
208           CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
209           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
210 #ifdef CONFIG_LS2080A
211         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
212           CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
213           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
214 #endif
215         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
216           CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
217           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
218         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
219           CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
220           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
221         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
222           CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
223           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
224         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
225           CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
226           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
227 #elif defined(CONFIG_FSL_LSCH2)
228         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
229           CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
230           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
231         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
232           CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
233           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
234         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
235           CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
236         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
237           CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
238           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
239         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
240           CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
241           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
242         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
243           CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
244         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
245           CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
246           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
247         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
248           CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
249           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
250         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
251           CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
252           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
253         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
254           CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
255           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
256         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
257           CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
258           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
259         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
260           CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
261           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
262         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
263           CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
264           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
265 #endif
266 };
267 #endif
268
269 int fsl_qoriq_core_to_cluster(unsigned int core);
270 u32 cpu_mask(void);
271 #endif /* _FSL_LAYERSCAPE_CPU_H */