armv8: layerscape: Allocate 66 MB DDR for secure memory
[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / cpu.h
1 /*
2  * Copyright 2017 NXP
3  * Copyright 2014-2015, Freescale Semiconductor
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #ifndef _FSL_LAYERSCAPE_CPU_H
9 #define _FSL_LAYERSCAPE_CPU_H
10
11 static struct cpu_type cpu_type_list[] = {
12         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
13         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
14         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
15         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
16         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
17         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
18         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
19         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
20         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
21         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
22         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
23         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
24         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
25         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
26         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
27         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
28         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
29         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
30         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
31 };
32
33 #ifndef CONFIG_SYS_DCACHE_OFF
34
35 #ifdef CONFIG_FSL_LSCH3
36 #define CONFIG_SYS_FSL_CCSR_BASE        0x00000000
37 #define CONFIG_SYS_FSL_CCSR_SIZE        0x10000000
38 #define CONFIG_SYS_FSL_QSPI_BASE1       0x20000000
39 #define CONFIG_SYS_FSL_QSPI_SIZE1       0x10000000
40 #define CONFIG_SYS_FSL_IFC_BASE1        0x30000000
41 #define CONFIG_SYS_FSL_IFC_SIZE1        0x10000000
42 #define CONFIG_SYS_FSL_IFC_SIZE1_1      0x400000
43 #define CONFIG_SYS_FSL_DRAM_BASE1       0x80000000
44 #define CONFIG_SYS_FSL_DRAM_SIZE1       0x80000000
45 #define CONFIG_SYS_FSL_QSPI_BASE2       0x400000000
46 #define CONFIG_SYS_FSL_QSPI_SIZE2       0x100000000
47 #define CONFIG_SYS_FSL_IFC_BASE2        0x500000000
48 #define CONFIG_SYS_FSL_IFC_SIZE2        0x100000000
49 #define CONFIG_SYS_FSL_DCSR_BASE        0x700000000
50 #define CONFIG_SYS_FSL_DCSR_SIZE        0x40000000
51 #define CONFIG_SYS_FSL_MC_BASE          0x80c000000
52 #define CONFIG_SYS_FSL_MC_SIZE          0x4000000
53 #define CONFIG_SYS_FSL_NI_BASE          0x810000000
54 #define CONFIG_SYS_FSL_NI_SIZE          0x8000000
55 #define CONFIG_SYS_FSL_QBMAN_BASE       0x818000000
56 #define CONFIG_SYS_FSL_QBMAN_SIZE       0x8000000
57 #define CONFIG_SYS_FSL_QBMAN_SIZE_1     0x4000000
58 #define CONFIG_SYS_PCIE1_PHYS_SIZE      0x200000000
59 #define CONFIG_SYS_PCIE2_PHYS_SIZE      0x200000000
60 #define CONFIG_SYS_PCIE3_PHYS_SIZE      0x200000000
61 #define CONFIG_SYS_PCIE4_PHYS_SIZE      0x200000000
62 #define CONFIG_SYS_FSL_WRIOP1_BASE      0x4300000000
63 #define CONFIG_SYS_FSL_WRIOP1_SIZE      0x100000000
64 #define CONFIG_SYS_FSL_AIOP1_BASE       0x4b00000000
65 #define CONFIG_SYS_FSL_AIOP1_SIZE       0x100000000
66 #define CONFIG_SYS_FSL_PEBUF_BASE       0x4c00000000
67 #define CONFIG_SYS_FSL_PEBUF_SIZE       0x400000000
68 #define CONFIG_SYS_FSL_DRAM_BASE2       0x8080000000
69 #define CONFIG_SYS_FSL_DRAM_SIZE2       0x7F80000000
70 #elif defined(CONFIG_FSL_LSCH2)
71 #define CONFIG_SYS_FSL_BOOTROM_BASE     0x0
72 #define CONFIG_SYS_FSL_BOOTROM_SIZE     0x1000000
73 #define CONFIG_SYS_FSL_CCSR_BASE        0x1000000
74 #define CONFIG_SYS_FSL_CCSR_SIZE        0xf000000
75 #define CONFIG_SYS_FSL_DCSR_BASE        0x20000000
76 #define CONFIG_SYS_FSL_DCSR_SIZE        0x4000000
77 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
78 #define CONFIG_SYS_FSL_QSPI_SIZE        0x20000000
79 #define CONFIG_SYS_FSL_IFC_BASE         0x60000000
80 #define CONFIG_SYS_FSL_IFC_SIZE         0x20000000
81 #define CONFIG_SYS_FSL_DRAM_BASE1       0x80000000
82 #define CONFIG_SYS_FSL_DRAM_SIZE1       0x80000000
83 #define CONFIG_SYS_FSL_QBMAN_BASE       0x500000000
84 #define CONFIG_SYS_FSL_QBMAN_SIZE       0x10000000
85 #define CONFIG_SYS_FSL_DRAM_BASE2       0x880000000
86 #define CONFIG_SYS_FSL_DRAM_SIZE2       0x780000000     /* 30GB */
87 #define CONFIG_SYS_PCIE1_PHYS_SIZE      0x800000000
88 #define CONFIG_SYS_PCIE2_PHYS_SIZE      0x800000000
89 #define CONFIG_SYS_PCIE3_PHYS_SIZE      0x800000000
90 #define CONFIG_SYS_FSL_DRAM_BASE3       0x8800000000
91 #define CONFIG_SYS_FSL_DRAM_SIZE3       0x7800000000    /* 480GB */
92 #endif
93
94 #define EARLY_PGTABLE_SIZE 0x5000
95 static struct mm_region early_map[] = {
96 #ifdef CONFIG_FSL_LSCH3
97         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
98           CONFIG_SYS_FSL_CCSR_SIZE,
99           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
100           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
101         },
102         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
103           SYS_FSL_OCRAM_SPACE_SIZE,
104           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
105         },
106         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
107           CONFIG_SYS_FSL_QSPI_SIZE1,
108           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
109 #ifdef CONFIG_FSL_IFC
110         /* For IFC Region #1, only the first 4MB is cache-enabled */
111         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
112           CONFIG_SYS_FSL_IFC_SIZE1_1,
113           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
114         },
115         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
116           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
117           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
118           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
119         },
120         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
121           CONFIG_SYS_FSL_IFC_SIZE1,
122           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
123         },
124 #endif
125         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
126           CONFIG_SYS_FSL_DRAM_SIZE1,
127 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
128           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
129 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
130           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
131 #endif
132           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
133         },
134 #ifdef CONFIG_FSL_IFC
135         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
136         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
137           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
138           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
139         },
140 #endif
141         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
142           CONFIG_SYS_FSL_DCSR_SIZE,
143           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
144           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
145         },
146         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
147           CONFIG_SYS_FSL_DRAM_SIZE2,
148           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
149           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
150         },
151 #elif defined(CONFIG_FSL_LSCH2)
152         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
153           CONFIG_SYS_FSL_CCSR_SIZE,
154           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
155           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
156         },
157         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
158           SYS_FSL_OCRAM_SPACE_SIZE,
159           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
160         },
161         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
162           CONFIG_SYS_FSL_DCSR_SIZE,
163           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
164           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
165         },
166         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
167           CONFIG_SYS_FSL_QSPI_SIZE,
168           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
169         },
170 #ifdef CONFIG_FSL_IFC
171         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
172           CONFIG_SYS_FSL_IFC_SIZE,
173           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
174         },
175 #endif
176         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
177           CONFIG_SYS_FSL_DRAM_SIZE1,
178 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
179           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
180 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
181           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
182 #endif
183           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
184         },
185         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
186           CONFIG_SYS_FSL_DRAM_SIZE2,
187           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
188           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
189         },
190 #endif
191         {},     /* list terminator */
192 };
193
194 static struct mm_region final_map[] = {
195 #ifdef CONFIG_FSL_LSCH3
196         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
197           CONFIG_SYS_FSL_CCSR_SIZE,
198           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
199           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
200         },
201         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
202           SYS_FSL_OCRAM_SPACE_SIZE,
203           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
204         },
205         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
206           CONFIG_SYS_FSL_DRAM_SIZE1,
207           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
208           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
209         },
210         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
211           CONFIG_SYS_FSL_QSPI_SIZE1,
212           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
213           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
214         },
215         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
216           CONFIG_SYS_FSL_QSPI_SIZE2,
217           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
218           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
219         },
220 #ifdef CONFIG_FSL_IFC
221         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
222           CONFIG_SYS_FSL_IFC_SIZE2,
223           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
224           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
225         },
226 #endif
227         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
228           CONFIG_SYS_FSL_DCSR_SIZE,
229           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
230           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
231         },
232         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
233           CONFIG_SYS_FSL_MC_SIZE,
234           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
235           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
236         },
237         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
238           CONFIG_SYS_FSL_NI_SIZE,
239           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
240           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
241         },
242         /* For QBMAN portal, only the first 64MB is cache-enabled */
243         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
244           CONFIG_SYS_FSL_QBMAN_SIZE_1,
245           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
246           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
247         },
248         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
249           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
250           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
251           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
252           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
253         },
254         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
255           CONFIG_SYS_PCIE1_PHYS_SIZE,
256           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
257           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
258         },
259         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
260           CONFIG_SYS_PCIE2_PHYS_SIZE,
261           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
262           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
263         },
264         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
265           CONFIG_SYS_PCIE3_PHYS_SIZE,
266           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
267           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
268         },
269 #ifdef CONFIG_ARCH_LS2080A
270         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
271           CONFIG_SYS_PCIE4_PHYS_SIZE,
272           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
273           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
274         },
275 #endif
276         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
277           CONFIG_SYS_FSL_WRIOP1_SIZE,
278           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
279           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
280         },
281         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
282           CONFIG_SYS_FSL_AIOP1_SIZE,
283           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
284           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
285         },
286         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
287           CONFIG_SYS_FSL_PEBUF_SIZE,
288           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
289           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
290         },
291         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
292           CONFIG_SYS_FSL_DRAM_SIZE2,
293           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
294           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
295         },
296 #elif defined(CONFIG_FSL_LSCH2)
297         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
298           CONFIG_SYS_FSL_BOOTROM_SIZE,
299           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
300           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
301         },
302         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
303           CONFIG_SYS_FSL_CCSR_SIZE,
304           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
305           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
306         },
307         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
308           SYS_FSL_OCRAM_SPACE_SIZE,
309           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
310         },
311         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
312           CONFIG_SYS_FSL_DCSR_SIZE,
313           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
314           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
315         },
316         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
317           CONFIG_SYS_FSL_QSPI_SIZE,
318           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
319           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
320         },
321 #ifdef CONFIG_FSL_IFC
322         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
323           CONFIG_SYS_FSL_IFC_SIZE,
324           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
325         },
326 #endif
327         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
328           CONFIG_SYS_FSL_DRAM_SIZE1,
329           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
330           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
331         },
332         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
333           CONFIG_SYS_FSL_QBMAN_SIZE,
334           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
335           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
336         },
337         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
338           CONFIG_SYS_FSL_DRAM_SIZE2,
339           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
340           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
341         },
342         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
343           CONFIG_SYS_PCIE1_PHYS_SIZE,
344           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
345           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
346         },
347         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
348           CONFIG_SYS_PCIE2_PHYS_SIZE,
349           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
350           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
351         },
352         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
353           CONFIG_SYS_PCIE3_PHYS_SIZE,
354           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
355           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
356         },
357         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
358           CONFIG_SYS_FSL_DRAM_SIZE3,
359           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
360           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
361         },
362 #endif
363 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
364         {},     /* space holder for secure mem */
365 #endif
366         {},
367 };
368 #endif  /* !CONFIG_SYS_DCACHE_OFF */
369
370 int fsl_qoriq_core_to_cluster(unsigned int core);
371 u32 cpu_mask(void);
372
373 #endif /* _FSL_LAYERSCAPE_CPU_H */