arch/arm/include/asm/arch-fsl-layerscape/cpu.h

   1 /*
   2  * Copyright 2014-2015, Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _FSL_LAYERSCAPE_CPU_H
   8 #define _FSL_LAYERSCAPE_CPU_H
   9
  10 static struct cpu_type cpu_type_list[] = {
  11         CPU_TYPE_ENTRY(LS2085, LS2085, 8),
  12         CPU_TYPE_ENTRY(LS2080, LS2080, 8),
  13         CPU_TYPE_ENTRY(LS2045, LS2045, 4),
  14         CPU_TYPE_ENTRY(LS1043, LS1043, 4),
  15 };
  16
  17 #ifndef CONFIG_SYS_DCACHE_OFF
  18
  19 #define SECTION_SHIFT_L0                39UL
  20 #define SECTION_SHIFT_L1                30UL
  21 #define SECTION_SHIFT_L2                21UL
  22 #define BLOCK_SIZE_L0                   0x8000000000
  23 #define BLOCK_SIZE_L1                   0x40000000
  24 #define BLOCK_SIZE_L2                   0x200000
  25 #define NUM_OF_ENTRY                    512
  26 #define TCR_EL2_PS_40BIT                (2 << 16)
  27
  28 #define LAYERSCAPE_VA_BITS              (40)
  29 #define LAYERSCAPE_TCR          (TCR_TG0_4K             | \
  30                                 TCR_EL2_PS_40BIT        | \
  31                                 TCR_SHARED_NON          | \
  32                                 TCR_ORGN_NC             | \
  33                                 TCR_IRGN_NC             | \
  34                                 TCR_T0SZ(LAYERSCAPE_VA_BITS))
  35 #define LAYERSCAPE_TCR_FINAL    (TCR_TG0_4K             | \
  36                                 TCR_EL2_PS_40BIT        | \
  37                                 TCR_SHARED_OUTER        | \
  38                                 TCR_ORGN_WBWA           | \
  39                                 TCR_IRGN_WBWA           | \
  40                                 TCR_T0SZ(LAYERSCAPE_VA_BITS))
  41
  42 #ifdef CONFIG_FSL_LSCH3
  43 #define CONFIG_SYS_FSL_CCSR_BASE        0x00000000
  44 #define CONFIG_SYS_FSL_CCSR_SIZE        0x10000000
  45 #define CONFIG_SYS_FSL_QSPI_BASE1       0x20000000
  46 #define CONFIG_SYS_FSL_QSPI_SIZE1       0x10000000
  47 #define CONFIG_SYS_FSL_IFC_BASE1        0x30000000
  48 #define CONFIG_SYS_FSL_IFC_SIZE1        0x10000000
  49 #define CONFIG_SYS_FSL_IFC_SIZE1_1      0x400000
  50 #define CONFIG_SYS_FSL_DRAM_BASE1       0x80000000
  51 #define CONFIG_SYS_FSL_DRAM_SIZE1       0x80000000
  52 #define CONFIG_SYS_FSL_QSPI_BASE2       0x400000000
  53 #define CONFIG_SYS_FSL_QSPI_SIZE2       0x100000000
  54 #define CONFIG_SYS_FSL_IFC_BASE2        0x500000000
  55 #define CONFIG_SYS_FSL_IFC_SIZE2        0x100000000
  56 #define CONFIG_SYS_FSL_DCSR_BASE        0x700000000
  57 #define CONFIG_SYS_FSL_DCSR_SIZE        0x40000000
  58 #define CONFIG_SYS_FSL_MC_BASE          0x80c000000
  59 #define CONFIG_SYS_FSL_MC_SIZE          0x4000000
  60 #define CONFIG_SYS_FSL_NI_BASE          0x810000000
  61 #define CONFIG_SYS_FSL_NI_SIZE          0x8000000
  62 #define CONFIG_SYS_FSL_QBMAN_BASE       0x818000000
  63 #define CONFIG_SYS_FSL_QBMAN_SIZE       0x8000000
  64 #define CONFIG_SYS_FSL_QBMAN_SIZE_1     0x4000000
  65 #define CONFIG_SYS_PCIE1_PHYS_SIZE      0x200000000
  66 #define CONFIG_SYS_PCIE2_PHYS_SIZE      0x200000000
  67 #define CONFIG_SYS_PCIE3_PHYS_SIZE      0x200000000
  68 #define CONFIG_SYS_PCIE4_PHYS_SIZE      0x200000000
  69 #define CONFIG_SYS_FSL_WRIOP1_BASE      0x4300000000
  70 #define CONFIG_SYS_FSL_WRIOP1_SIZE      0x100000000
  71 #define CONFIG_SYS_FSL_AIOP1_BASE       0x4b00000000
  72 #define CONFIG_SYS_FSL_AIOP1_SIZE       0x100000000
  73 #define CONFIG_SYS_FSL_PEBUF_BASE       0x4c00000000
  74 #define CONFIG_SYS_FSL_PEBUF_SIZE       0x400000000
  75 #define CONFIG_SYS_FSL_DRAM_BASE2       0x8080000000
  76 #define CONFIG_SYS_FSL_DRAM_SIZE2       0x7F80000000
  77 #elif defined(CONFIG_FSL_LSCH2)
  78 #define CONFIG_SYS_FSL_BOOTROM_BASE     0x0
  79 #define CONFIG_SYS_FSL_BOOTROM_SIZE     0x1000000
  80 #define CONFIG_SYS_FSL_CCSR_BASE        0x1000000
  81 #define CONFIG_SYS_FSL_CCSR_SIZE        0xf000000
  82 #define CONFIG_SYS_FSL_DCSR_BASE        0x20000000
  83 #define CONFIG_SYS_FSL_DCSR_SIZE        0x4000000
  84 #define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
  85 #define CONFIG_SYS_FSL_QSPI_SIZE        0x20000000
  86 #define CONFIG_SYS_FSL_IFC_BASE         0x60000000
  87 #define CONFIG_SYS_FSL_IFC_SIZE         0x20000000
  88 #define CONFIG_SYS_FSL_DRAM_BASE1       0x80000000
  89 #define CONFIG_SYS_FSL_DRAM_SIZE1       0x80000000
  90 #define CONFIG_SYS_FSL_QBMAN_BASE       0x500000000
  91 #define CONFIG_SYS_FSL_QBMAN_SIZE       0x10000000
  92 #define CONFIG_SYS_FSL_DRAM_BASE2       0x880000000
  93 #define CONFIG_SYS_FSL_DRAM_SIZE2       0x780000000     /* 30GB */
  94 #define CONFIG_SYS_PCIE1_PHYS_SIZE      0x800000000
  95 #define CONFIG_SYS_PCIE2_PHYS_SIZE      0x800000000
  96 #define CONFIG_SYS_PCIE3_PHYS_SIZE      0x800000000
  97 #define CONFIG_SYS_FSL_DRAM_BASE3       0x8800000000
  98 #define CONFIG_SYS_FSL_DRAM_SIZE3       0x7800000000    /* 480GB */
  99 #endif
 100
 101 struct sys_mmu_table {
 102         u64 virt_addr;
 103         u64 phys_addr;
 104         u64 size;
 105         u64 memory_type;
 106         u64 share;
 107 };
 108
 109 struct table_info {
 110         u64 *ptr;
 111         u64 table_base;
 112         u64 entry_size;
 113 };
 114
 115 static const struct sys_mmu_table early_mmu_table[] = {
 116 #ifdef CONFIG_FSL_LSCH3
 117         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 118           CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 119         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 120           CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
 121         /* For IFC Region #1, only the first 4MB is cache-enabled */
 122         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 123           CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
 124         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 125           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 126           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 127           MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 128         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 129           CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 130         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 131           CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 132         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 133           CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 134         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 135           CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 136 #elif defined(CONFIG_FSL_LSCH2)
 137         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 138           CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 139         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 140           CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
 141         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 142           CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 143         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 144           CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 145         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 146           CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 147         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 148           CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 149 #endif
 150 };
 151
 152 static const struct sys_mmu_table final_mmu_table[] = {
 153 #ifdef CONFIG_FSL_LSCH3
 154         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 155           CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 156         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 157           CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
 158         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 159           CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 160         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 161           CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 162         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 163           CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 164         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 165           CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 166         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 167           CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 168         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 169           CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 170         /* For QBMAN portal, only the first 64MB is cache-enabled */
 171         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 172           CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
 173         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 174           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 175           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 176           MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 177         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 178           CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 179         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 180           CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 181         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 182           CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 183 #ifdef CONFIG_LS2085A
 184         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 185           CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 186 #endif
 187         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 188           CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 189         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 190           CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 191         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 192           CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 193         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 194           CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 195 #elif defined(CONFIG_FSL_LSCH2)
 196         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 197           CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 198         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 199           CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 200         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 201           CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
 202         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 203           CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 204         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 205           CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 206         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 207           CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 208         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 209           CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
 210           PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
 211         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 212           CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 213         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 214           CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 215         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 216           CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 217         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 218           CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 219         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 220           CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
 221         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 222           CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 223 #endif
 224 };
 225 #endif
 226
 227 int fsl_qoriq_core_to_cluster(unsigned int core);
 228 u32 cpu_mask(void);
 229 #endif /* _FSL_LAYERSCAPE_CPU_H */