1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2018 NXP
4 * Copyright 2015, Freescale Semiconductor
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
16 * Reserve secure memory
17 * To be aligned with MMU block size
19 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
22 #ifdef CONFIG_ARCH_LS2080A
23 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
24 #define SRDS_MAX_LANES 8
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
26 #ifndef L1_CACHE_BYTES
27 #define L1_CACHE_SHIFT 6
28 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
36 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
37 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
39 #define CONFIG_SYS_FSL_CCSR_GUR_LE
40 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
41 #define CONFIG_SYS_FSL_ESDHC_LE
42 #define CONFIG_SYS_FSL_IFC_LE
43 #define CONFIG_SYS_FSL_PEX_LUT_LE
45 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
47 /* Generic Interrupt Controller Definitions */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
55 #define CONFIG_SYS_FSL_SFP_VER_3_4
56 #define CONFIG_SYS_FSL_SFP_LE
57 #define CONFIG_SYS_FSL_SRK_LE
59 /* Security Monitor */
60 #define CONFIG_SYS_FSL_SEC_MON_LE
63 #define CONFIG_ESBC_HDR_LS
66 #define CONFIG_SYS_FSL_CCSR_GUR_LE
68 /* Cache Coherent Interconnect */
69 #define CCI_MN_BASE 0x04000000
70 #define CCI_MN_RNF_NODEID_LIST 0x180
71 #define CCI_MN_DVM_DOMAIN_CTL 0x200
72 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
74 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
75 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
76 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
77 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
78 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
79 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
81 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
82 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
83 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
84 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
85 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
86 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
88 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
89 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
90 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
92 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
94 /* TZ Protection Controller Definitions */
95 #define TZPC_BASE 0x02200000
96 #define TZPCR0SIZE_BASE (TZPC_BASE)
97 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
98 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
99 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
100 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
101 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
102 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
103 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
104 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
105 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
107 #define DCSR_CGACRE5 0x700070914ULL
108 #define EPU_EPCMPR5 0x700060914ULL
109 #define EPU_EPCCR5 0x700060814ULL
110 #define EPU_EPSMCR5 0x700060228ULL
111 #define EPU_EPECR5 0x700060314ULL
112 #define EPU_EPCTR5 0x700060a14ULL
113 #define EPU_EPGCR 0x700060000ULL
115 #define CONFIG_SYS_FSL_ERRATUM_A008751
117 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
119 #elif defined(CONFIG_ARCH_LS1088A)
120 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
121 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
123 #define CONFIG_SYS_PAGE_SIZE 0x10000
125 #define SRDS_MAX_LANES 4
127 /* TZ Protection Controller Definitions */
128 #define TZPC_BASE 0x02200000
129 #define TZPCR0SIZE_BASE (TZPC_BASE)
130 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
131 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
132 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
133 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
134 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
135 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
136 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
137 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
138 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
140 /* Generic Interrupt Controller Definitions */
141 #define GICD_BASE 0x06000000
142 #define GICR_BASE 0x06100000
144 /* SMMU Defintions */
145 #define SMMU_BASE 0x05000000 /* GR0 Base */
148 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
149 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
151 #define CONFIG_SYS_FSL_CCSR_GUR_LE
152 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
153 #define CONFIG_SYS_FSL_ESDHC_LE
154 #define CONFIG_SYS_FSL_IFC_LE
155 #define CONFIG_SYS_FSL_PEX_LUT_LE
157 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
160 #define CONFIG_SYS_FSL_SFP_VER_3_4
161 #define CONFIG_SYS_FSL_SFP_LE
162 #define CONFIG_SYS_FSL_SRK_LE
164 /* Security Monitor */
165 #define CONFIG_SYS_FSL_SEC_MON_LE
168 #define CONFIG_ESBC_HDR_LS
171 #define CONFIG_SYS_FSL_CCSR_GUR_LE
172 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
173 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
174 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
175 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
177 /* LX2160A Soc Support */
178 #elif defined(CONFIG_ARCH_LX2160A)
179 #define TZPC_BASE 0x02200000
180 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
181 #define CONFIG_SYS_I2C
182 #define CONFIG_SYS_I2C_EARLY_INIT
183 #define SRDS_MAX_LANES 8
184 #ifndef L1_CACHE_BYTES
185 #define L1_CACHE_SHIFT 6
186 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
188 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
189 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
190 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
192 #define CONFIG_SYS_PAGE_SIZE 0x10000
194 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
195 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
196 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
199 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
200 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
202 #define CONFIG_SYS_FSL_CCSR_GUR_LE
203 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
204 #define CONFIG_SYS_FSL_ESDHC_LE
205 #define CONFIG_SYS_FSL_PEX_LUT_LE
207 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
209 /* Generic Interrupt Controller Definitions */
210 #define GICD_BASE 0x06000000
211 #define GICR_BASE 0x06200000
213 /* SMMU Definitions */
214 #define SMMU_BASE 0x05000000 /* GR0 Base */
217 #define CONFIG_SYS_FSL_SFP_VER_3_4
218 #define CONFIG_SYS_FSL_SFP_LE
219 #define CONFIG_SYS_FSL_SRK_LE
221 /* Security Monitor */
222 #define CONFIG_SYS_FSL_SEC_MON_LE
225 #define CONFIG_ESBC_HDR_LS
228 #define CONFIG_SYS_FSL_CCSR_GUR_LE
230 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
232 #elif defined(CONFIG_ARCH_LS1028A)
233 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
234 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
236 #define CONFIG_FSL_TZPC_BP147
237 #define CONFIG_FSL_TZASC_400
239 /* TZ Protection Controller Definitions */
240 #define TZPC_BASE 0x02200000
241 #define TZPCR0SIZE_BASE (TZPC_BASE)
242 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
243 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
244 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
245 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
246 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
247 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
248 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
249 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
250 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
252 #define SRDS_MAX_LANES 4
254 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
255 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
256 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
258 /* Generic Interrupt Controller Definitions */
259 #define GICD_BASE 0x06000000
260 #define GICR_BASE 0x06040000
262 /* SMMU Definitions */
263 #define SMMU_BASE 0x05000000 /* GR0 Base */
266 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
267 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
269 #define CONFIG_SYS_FSL_CCSR_GUR_LE
270 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
271 #define CONFIG_SYS_FSL_ESDHC_LE
272 #define CONFIG_SYS_FSL_PEX_LUT_LE
274 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
277 #define CONFIG_SYS_FSL_SFP_VER_3_4
278 #define CONFIG_SYS_FSL_SFP_LE
279 #define CONFIG_SYS_FSL_SRK_LE
282 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
284 /* Security Monitor */
285 #define CONFIG_SYS_FSL_SEC_MON_LE
288 #define CONFIG_ESBC_HDR_LS
291 #define CONFIG_SYS_FSL_CCSR_GUR_LE
293 #elif defined(CONFIG_FSL_LSCH2)
294 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
295 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
296 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
298 #define DCSR_DCFG_SBEESR2 0x20140534
299 #define DCSR_DCFG_MBEESR2 0x20140544
301 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
302 #define CONFIG_SYS_FSL_ESDHC_BE
303 #define CONFIG_SYS_FSL_WDOG_BE
304 #define CONFIG_SYS_FSL_DSPI_BE
305 #define CONFIG_SYS_FSL_QSPI_BE
306 #define CONFIG_SYS_FSL_CCSR_GUR_BE
307 #define CONFIG_SYS_FSL_PEX_LUT_BE
310 #ifdef CONFIG_ARCH_LS1043A
311 #define CONFIG_SYS_FMAN_V3
312 #define CONFIG_SYS_FSL_QMAN_V3
313 #define CONFIG_SYS_NUM_FMAN 1
314 #define CONFIG_SYS_NUM_FM1_DTSEC 7
315 #define CONFIG_SYS_NUM_FM1_10GEC 1
316 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
317 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
319 #define QE_MURAM_SIZE 0x6000UL
320 #define MAX_QE_RISC 1
321 #define QE_NUM_OF_SNUM 28
323 #define CONFIG_SYS_FSL_IFC_BE
324 #define CONFIG_SYS_FSL_SFP_VER_3_2
325 #define CONFIG_SYS_FSL_SEC_MON_BE
326 #define CONFIG_SYS_FSL_SFP_BE
327 #define CONFIG_SYS_FSL_SRK_LE
328 #define CONFIG_KEY_REVOCATION
330 /* SMMU Defintions */
331 #define SMMU_BASE 0x09000000
333 /* Generic Interrupt Controller Definitions */
334 #define GICD_BASE 0x01401000
335 #define GICC_BASE 0x01402000
336 #define GICH_BASE 0x01404000
337 #define GICV_BASE 0x01406000
338 #define GICD_SIZE 0x1000
339 #define GICC_SIZE 0x2000
340 #define GICH_SIZE 0x2000
341 #define GICV_SIZE 0x2000
342 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
343 #define GICD_BASE_64K 0x01410000
344 #define GICC_BASE_64K 0x01420000
345 #define GICH_BASE_64K 0x01440000
346 #define GICV_BASE_64K 0x01460000
347 #define GICD_SIZE_64K 0x10000
348 #define GICC_SIZE_64K 0x20000
349 #define GICH_SIZE_64K 0x20000
350 #define GICV_SIZE_64K 0x20000
353 #define DCFG_CCSR_SVR 0x1ee00a4
356 #define GIC_ADDR_BIT 31
357 #define SCFG_GIC400_ALIGN 0x1570188
359 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
361 #elif defined(CONFIG_ARCH_LS1012A)
362 #define GICD_BASE 0x01401000
363 #define GICC_BASE 0x01402000
364 #define CONFIG_SYS_FSL_SFP_VER_3_2
365 #define CONFIG_SYS_FSL_SEC_MON_BE
366 #define CONFIG_SYS_FSL_SFP_BE
367 #define CONFIG_SYS_FSL_SRK_LE
368 #define CONFIG_KEY_REVOCATION
369 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
370 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
371 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
373 #elif defined(CONFIG_ARCH_LS1046A)
374 #define CONFIG_SYS_FMAN_V3
375 #define CONFIG_SYS_FSL_QMAN_V3
376 #define CONFIG_SYS_NUM_FMAN 1
377 #define CONFIG_SYS_NUM_FM1_DTSEC 8
378 #define CONFIG_SYS_NUM_FM1_10GEC 2
379 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
380 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
382 #define CONFIG_SYS_FSL_IFC_BE
383 #define CONFIG_SYS_FSL_SFP_VER_3_2
384 #define CONFIG_SYS_FSL_SEC_MON_BE
385 #define CONFIG_SYS_FSL_SFP_BE
386 #define CONFIG_SYS_FSL_SRK_LE
387 #define CONFIG_KEY_REVOCATION
389 /* SMMU Defintions */
390 #define SMMU_BASE 0x09000000
392 /* Generic Interrupt Controller Definitions */
393 #define GICD_BASE 0x01410000
394 #define GICC_BASE 0x01420000
396 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
398 #error SoC not defined
402 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */