2 * Copyright 2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
15 #ifdef CONFIG_SYS_FSL_DDR4
16 #define CONFIG_SYS_FSL_DDRC_GEN4
18 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
21 #ifndef CONFIG_ARCH_LS1012A
22 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
23 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
27 * Reserve secure memory
28 * To be aligned with MMU block size
30 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
33 #define CONFIG_MAX_CPUS 16
34 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
35 #define CONFIG_NUM_DDR_CONTROLLERS 3
36 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
37 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
38 #define SRDS_MAX_LANES 8
39 #define CONFIG_SYS_FSL_SRDS_1
40 #define CONFIG_SYS_FSL_SRDS_2
41 #define CONFIG_SYS_PAGE_SIZE 0x10000
42 #ifndef L1_CACHE_BYTES
43 #define L1_CACHE_SHIFT 6
44 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
47 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
48 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
51 #define CONFIG_SYS_FSL_DDR_LE
52 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
53 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
55 #define CONFIG_SYS_FSL_CCSR_GUR_LE
56 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
57 #define CONFIG_SYS_FSL_ESDHC_LE
58 #define CONFIG_SYS_FSL_IFC_LE
59 #define CONFIG_SYS_FSL_PEX_LUT_LE
61 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
63 /* Generic Interrupt Controller Definitions */
64 #define GICD_BASE 0x06000000
65 #define GICR_BASE 0x06100000
68 #define SMMU_BASE 0x05000000 /* GR0 Base */
71 #define CONFIG_SYS_FSL_SFP_VER_3_4
72 #define CONFIG_SYS_FSL_SFP_LE
73 #define CONFIG_SYS_FSL_SRK_LE
76 #define CONFIG_SYS_FSL_SEC_LE
77 #define CONFIG_SYS_FSL_SEC_COMPAT 5
79 /* Security Monitor */
80 #define CONFIG_SYS_FSL_SEC_MON_LE
83 #define CONFIG_ESBC_HDR_LS
86 #define CONFIG_SYS_FSL_CCSR_GUR_LE
88 /* Cache Coherent Interconnect */
89 #define CCI_MN_BASE 0x04000000
90 #define CCI_MN_RNF_NODEID_LIST 0x180
91 #define CCI_MN_DVM_DOMAIN_CTL 0x200
92 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
94 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
95 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
96 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
97 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
98 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
99 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
101 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
102 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
103 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
104 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
105 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
106 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
108 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
109 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
110 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
112 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
114 /* TZ Protection Controller Definitions */
115 #define TZPC_BASE 0x02200000
116 #define TZPCR0SIZE_BASE (TZPC_BASE)
117 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
118 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
119 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
120 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
121 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
122 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
123 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
124 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
125 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
127 #define DCSR_CGACRE5 0x700070914ULL
128 #define EPU_EPCMPR5 0x700060914ULL
129 #define EPU_EPCCR5 0x700060814ULL
130 #define EPU_EPSMCR5 0x700060228ULL
131 #define EPU_EPECR5 0x700060314ULL
132 #define EPU_EPCTR5 0x700060a14ULL
133 #define EPU_EPGCR 0x700060000ULL
135 #define CONFIG_SYS_FSL_ERRATUM_A008336
136 #define CONFIG_SYS_FSL_ERRATUM_A008511
137 #define CONFIG_SYS_FSL_ERRATUM_A008514
138 #define CONFIG_SYS_FSL_ERRATUM_A008585
139 #define CONFIG_SYS_FSL_ERRATUM_A008751
140 #define CONFIG_SYS_FSL_ERRATUM_A009635
141 #define CONFIG_SYS_FSL_ERRATUM_A009663
142 #define CONFIG_SYS_FSL_ERRATUM_A009801
143 #define CONFIG_SYS_FSL_ERRATUM_A009803
144 #define CONFIG_SYS_FSL_ERRATUM_A009942
145 #define CONFIG_SYS_FSL_ERRATUM_A010165
147 /* ARM A57 CORE ERRATA */
148 #define CONFIG_ARM_ERRATA_826974
149 #define CONFIG_ARM_ERRATA_828024
150 #define CONFIG_ARM_ERRATA_829520
151 #define CONFIG_ARM_ERRATA_833471
153 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
154 #elif defined(CONFIG_FSL_LSCH2)
155 #define CONFIG_NUM_DDR_CONTROLLERS 1
156 #define CONFIG_SYS_FSL_SEC_COMPAT 5
157 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
158 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
159 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
161 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
162 #define CONFIG_SYS_FSL_ESDHC_BE
163 #define CONFIG_SYS_FSL_WDOG_BE
164 #define CONFIG_SYS_FSL_DSPI_BE
165 #define CONFIG_SYS_FSL_QSPI_BE
166 #define CONFIG_SYS_FSL_CCSR_GUR_BE
167 #define CONFIG_SYS_FSL_PEX_LUT_BE
168 #define CONFIG_SYS_FSL_SEC_BE
170 #define CONFIG_SYS_FSL_SRDS_1
173 #ifdef CONFIG_LS1043A
174 #define CONFIG_MAX_CPUS 4
175 #define CONFIG_SYS_FMAN_V3
176 #define CONFIG_SYS_NUM_FMAN 1
177 #define CONFIG_SYS_NUM_FM1_DTSEC 7
178 #define CONFIG_SYS_NUM_FM1_10GEC 1
179 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
180 #define CONFIG_SYS_FSL_DDR_BE
181 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
182 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
184 #define QE_MURAM_SIZE 0x6000UL
185 #define MAX_QE_RISC 1
186 #define QE_NUM_OF_SNUM 28
188 #define CONFIG_SYS_FSL_IFC_BE
189 #define CONFIG_SYS_FSL_SFP_VER_3_2
190 #define CONFIG_SYS_FSL_SEC_MON_BE
191 #define CONFIG_SYS_FSL_SFP_BE
192 #define CONFIG_SYS_FSL_SRK_LE
193 #define CONFIG_KEY_REVOCATION
195 /* SMMU Defintions */
196 #define SMMU_BASE 0x09000000
198 /* Generic Interrupt Controller Definitions */
199 #define GICD_BASE 0x01401000
200 #define GICC_BASE 0x01402000
202 #define CONFIG_SYS_FSL_ERRATUM_A008850
203 #define CONFIG_SYS_FSL_ERRATUM_A009663
204 #define CONFIG_SYS_FSL_ERRATUM_A009929
205 #define CONFIG_SYS_FSL_ERRATUM_A009942
206 #define CONFIG_SYS_FSL_ERRATUM_A009660
207 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
208 #elif defined(CONFIG_ARCH_LS1012A)
209 #define CONFIG_MAX_CPUS 1
210 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
212 #define GICD_BASE 0x01401000
213 #define GICC_BASE 0x01402000
214 #elif defined(CONFIG_ARCH_LS1046A)
215 #define CONFIG_MAX_CPUS 4
216 #define CONFIG_SYS_FMAN_V3
217 #define CONFIG_SYS_NUM_FMAN 1
218 #define CONFIG_SYS_NUM_FM1_DTSEC 8
219 #define CONFIG_SYS_NUM_FM1_10GEC 2
220 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
221 #define CONFIG_SYS_FSL_DDR_BE
222 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
223 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
225 #define CONFIG_SYS_FSL_SRDS_2
226 #define CONFIG_SYS_FSL_IFC_BE
227 #define CONFIG_SYS_FSL_SFP_VER_3_2
228 #define CONFIG_SYS_FSL_SNVS_LE
229 #define CONFIG_SYS_FSL_SFP_BE
230 #define CONFIG_SYS_FSL_SRK_LE
231 #define CONFIG_KEY_REVOCATION
233 /* SMMU Defintions */
234 #define SMMU_BASE 0x09000000
236 /* Generic Interrupt Controller Definitions */
237 #define GICD_BASE 0x01410000
238 #define GICC_BASE 0x01420000
240 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
242 #define CONFIG_SYS_FSL_ERRATUM_A008511
243 #define CONFIG_SYS_FSL_ERRATUM_A009801
244 #define CONFIG_SYS_FSL_ERRATUM_A009803
245 #define CONFIG_SYS_FSL_ERRATUM_A009942
246 #define CONFIG_SYS_FSL_ERRATUM_A010165
248 #error SoC not defined
252 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */