2 * Copyright 2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
16 * Reserve secure memory
17 * To be aligned with MMU block size
19 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
22 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
23 #define SRDS_MAX_LANES 8
24 #define CONFIG_SYS_PAGE_SIZE 0x10000
25 #ifndef L1_CACHE_BYTES
26 #define L1_CACHE_SHIFT 6
27 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
28 #define CONFIG_FSL_TZASC_400
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
36 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
37 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
39 #define CONFIG_SYS_FSL_CCSR_GUR_LE
40 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
41 #define CONFIG_SYS_FSL_ESDHC_LE
42 #define CONFIG_SYS_FSL_IFC_LE
43 #define CONFIG_SYS_FSL_PEX_LUT_LE
45 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
47 /* Generic Interrupt Controller Definitions */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
55 #define CONFIG_SYS_FSL_SFP_VER_3_4
56 #define CONFIG_SYS_FSL_SFP_LE
57 #define CONFIG_SYS_FSL_SRK_LE
59 /* Security Monitor */
60 #define CONFIG_SYS_FSL_SEC_MON_LE
63 #define CONFIG_ESBC_HDR_LS
66 #define CONFIG_SYS_FSL_CCSR_GUR_LE
68 /* Cache Coherent Interconnect */
69 #define CCI_MN_BASE 0x04000000
70 #define CCI_MN_RNF_NODEID_LIST 0x180
71 #define CCI_MN_DVM_DOMAIN_CTL 0x200
72 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
74 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
75 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
76 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
77 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
78 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
79 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
81 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
82 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
83 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
84 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
85 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
86 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
88 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
89 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
90 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
92 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
94 /* TZ Protection Controller Definitions */
95 #define TZPC_BASE 0x02200000
96 #define TZPCR0SIZE_BASE (TZPC_BASE)
97 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
98 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
99 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
100 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
101 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
102 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
103 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
104 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
105 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
107 #define DCSR_CGACRE5 0x700070914ULL
108 #define EPU_EPCMPR5 0x700060914ULL
109 #define EPU_EPCCR5 0x700060814ULL
110 #define EPU_EPSMCR5 0x700060228ULL
111 #define EPU_EPECR5 0x700060314ULL
112 #define EPU_EPCTR5 0x700060a14ULL
113 #define EPU_EPGCR 0x700060000ULL
115 #define CONFIG_SYS_FSL_ERRATUM_A008751
117 /* ARM A57 CORE ERRATA */
118 #define CONFIG_ARM_ERRATA_826974
119 #define CONFIG_ARM_ERRATA_828024
120 #define CONFIG_ARM_ERRATA_829520
121 #define CONFIG_ARM_ERRATA_833471
123 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
124 #elif defined(CONFIG_FSL_LSCH2)
125 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
126 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
127 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
129 #define DCSR_DCFG_SBEESR2 0x20140534
130 #define DCSR_DCFG_MBEESR2 0x20140544
132 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
133 #define CONFIG_SYS_FSL_ESDHC_BE
134 #define CONFIG_SYS_FSL_WDOG_BE
135 #define CONFIG_SYS_FSL_DSPI_BE
136 #define CONFIG_SYS_FSL_QSPI_BE
137 #define CONFIG_SYS_FSL_CCSR_GUR_BE
138 #define CONFIG_SYS_FSL_PEX_LUT_BE
141 #ifdef CONFIG_LS1043A
142 #define CONFIG_SYS_FMAN_V3
143 #define CONFIG_SYS_NUM_FMAN 1
144 #define CONFIG_SYS_NUM_FM1_DTSEC 7
145 #define CONFIG_SYS_NUM_FM1_10GEC 1
146 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
147 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
149 #define QE_MURAM_SIZE 0x6000UL
150 #define MAX_QE_RISC 1
151 #define QE_NUM_OF_SNUM 28
153 #define CONFIG_SYS_FSL_IFC_BE
154 #define CONFIG_SYS_FSL_SFP_VER_3_2
155 #define CONFIG_SYS_FSL_SEC_MON_BE
156 #define CONFIG_SYS_FSL_SFP_BE
157 #define CONFIG_SYS_FSL_SRK_LE
158 #define CONFIG_KEY_REVOCATION
160 /* SMMU Defintions */
161 #define SMMU_BASE 0x09000000
163 /* Generic Interrupt Controller Definitions */
164 #define GICD_BASE 0x01401000
165 #define GICC_BASE 0x01402000
167 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
169 #elif defined(CONFIG_ARCH_LS1012A)
170 #define GICD_BASE 0x01401000
171 #define GICC_BASE 0x01402000
173 #elif defined(CONFIG_ARCH_LS1046A)
174 #define CONFIG_SYS_FMAN_V3
175 #define CONFIG_SYS_NUM_FMAN 1
176 #define CONFIG_SYS_NUM_FM1_DTSEC 8
177 #define CONFIG_SYS_NUM_FM1_10GEC 2
178 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
179 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
181 #define CONFIG_SYS_FSL_IFC_BE
182 #define CONFIG_SYS_FSL_SFP_VER_3_2
183 #define CONFIG_SYS_FSL_SNVS_LE
184 #define CONFIG_SYS_FSL_SFP_BE
185 #define CONFIG_SYS_FSL_SRK_LE
186 #define CONFIG_KEY_REVOCATION
188 /* SMMU Defintions */
189 #define SMMU_BASE 0x09000000
191 /* Generic Interrupt Controller Definitions */
192 #define GICD_BASE 0x01410000
193 #define GICC_BASE 0x01420000
195 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
198 #error SoC not defined
202 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */