2 * SAMSUNG EXYNOS USB HOST EHCI Controller
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Vivek Gautam <gautam.vivek@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __ASM_ARM_ARCH_EHCI_H__
11 #define __ASM_ARM_ARCH_EHCI_H__
15 #define HOST_CTRL0_PHYSWRSTALL (1 << 31)
16 #define HOST_CTRL0_COMMONON_N (1 << 9)
17 #define HOST_CTRL0_SIDDQ (1 << 6)
18 #define HOST_CTRL0_FORCESLEEP (1 << 5)
19 #define HOST_CTRL0_FORCESUSPEND (1 << 4)
20 #define HOST_CTRL0_WORDINTERFACE (1 << 3)
21 #define HOST_CTRL0_UTMISWRST (1 << 2)
22 #define HOST_CTRL0_LINKSWRST (1 << 1)
23 #define HOST_CTRL0_PHYSWRST (1 << 0)
25 #define HOST_CTRL0_FSEL_MASK (7 << 16)
27 #define EHCICTRL_ENAINCRXALIGN (1 << 29)
28 #define EHCICTRL_ENAINCR4 (1 << 28)
29 #define EHCICTRL_ENAINCR8 (1 << 27)
30 #define EHCICTRL_ENAINCR16 (1 << 26)
32 #define HSIC_CTRL_REFCLKSEL (0x2)
33 #define HSIC_CTRL_REFCLKSEL_MASK (0x3)
34 #define HSIC_CTRL_REFCLKSEL_SHIFT (23)
36 #define HSIC_CTRL_REFCLKDIV_12 (0x24)
37 #define HSIC_CTRL_REFCLKDIV_MASK (0x7f)
38 #define HSIC_CTRL_REFCLKDIV_SHIFT (16)
40 #define HSIC_CTRL_SIDDQ (0x1 << 6)
41 #define HSIC_CTRL_FORCESLEEP (0x1 << 5)
42 #define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
43 #define HSIC_CTRL_UTMISWRST (0x1 << 2)
44 #define HSIC_CTRL_PHYSWRST (0x1 << 0)
46 /* Register map for PHY control */
47 struct exynos_usb_phy {
48 unsigned int usbphyctrl0;
49 unsigned int usbphytune0;
50 unsigned int reserved1[2];
51 unsigned int hsicphyctrl1;
52 unsigned int hsicphytune1;
53 unsigned int reserved2[2];
54 unsigned int hsicphyctrl2;
55 unsigned int hsicphytune2;
56 unsigned int reserved3[2];
57 unsigned int ehcictrl;
58 unsigned int ohcictrl;
59 unsigned int usbotgsys;
60 unsigned int reserved4;
61 unsigned int usbotgtune;
64 /* Switch on the VBUS power. */
65 int board_usb_vbus_init(void);
67 #endif /* __ASM_ARM_ARCH_EHCI_H__ */