3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef _DV_PLL_DEFS_H_
24 #define _DV_PLL_DEFS_H_
27 unsigned int pid; /* 0x00 */
28 unsigned char rsvd0[224]; /* 0x04 */
29 unsigned int rstype; /* 0xe4 */
30 unsigned char rsvd1[24]; /* 0xe8 */
31 unsigned int pllctl; /* 0x100 */
32 unsigned char rsvd2[4]; /* 0x104 */
33 unsigned int secctl; /* 0x108 */
34 unsigned int rv; /* 0x10c */
35 unsigned int pllm; /* 0x110 */
36 unsigned int prediv; /* 0x114 */
37 unsigned int plldiv1; /* 0x118 */
38 unsigned int plldiv2; /* 0x11c */
39 unsigned int plldiv3; /* 0x120 */
40 unsigned int oscdiv1; /* 0x124 */
41 unsigned int postdiv; /* 0x128 */
42 unsigned int bpdiv; /* 0x12c */
43 unsigned char rsvd5[8]; /* 0x130 */
44 unsigned int pllcmd; /* 0x138 */
45 unsigned int pllstat; /* 0x13c */
46 unsigned int alnctl; /* 0x140 */
47 unsigned int dchange; /* 0x144 */
48 unsigned int cken; /* 0x148 */
49 unsigned int ckstat; /* 0x14c */
50 unsigned int systat; /* 0x150 */
51 unsigned char rsvd6[12]; /* 0x154 */
52 unsigned int plldiv4; /* 0x160 */
53 unsigned int plldiv5; /* 0x164 */
54 unsigned int plldiv6; /* 0x168 */
55 unsigned int plldiv7; /* 0x16C */
56 unsigned int plldiv8; /* 0x170 */
57 unsigned int plldiv9; /* 0x174 */
60 #define PLL_MASTER_LOCK (1 << 4)
62 #define PLLCTL_CLOCK_MODE_SHIFT 8
63 #define PLLCTL_PLLEN (1 << 0)
64 #define PLLCTL_PLLPWRDN (1 << 1)
65 #define PLLCTL_PLLRST (1 << 3)
66 #define PLLCTL_PLLDIS (1 << 4)
67 #define PLLCTL_PLLENSRC (1 << 5)
68 #define PLLCTL_RES_9 (1 << 8)
69 #define PLLCTL_EXTCLKSRC (1 << 9)
71 #define PLL_DIVEN (1 << 15)
72 #define PLL_POSTDEN PLL_DIVEN
74 #define PLL_SCSCFG3_DIV45PENA (1 << 2)
75 #define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
77 #define PLL_RSTYPE_POR (1 << 0)
78 #define PLL_RSTYPE_XWRST (1 << 1)
80 #define PLLSECCTL_TINITZ (1 << 16)
81 #define PLLSECCTL_TENABLE (1 << 17)
82 #define PLLSECCTL_TENABLEDIV (1 << 18)
83 #define PLLSECCTL_STOPMODE (1 << 22)
85 #define PLLCMD_GOSET (1 << 0)
86 #define PLLCMD_GOSTAT (1 << 0)
88 #define PLL0_LOCK 0x07000000
89 #define PLL1_LOCK 0x07000000
91 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
92 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
94 #define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
95 #define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
96 #define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
98 unsigned int davinci_clk_get(unsigned int div);
99 #endif /* _DV_PLL_DEFS_H_ */