2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * -------------------------------------------------------------------------
8 * linux/include/asm-arm/arch-davinci/hardware.h
10 * Copyright (C) 2006 Texas Instruments.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #ifndef __ASM_ARCH_HARDWARE_H
34 #define __ASM_ARCH_HARDWARE_H
37 #include <asm/sizes.h>
39 #define REG(addr) (*(volatile unsigned int *)(addr))
40 #define REG_P(addr) ((volatile unsigned int *)(addr))
42 typedef volatile unsigned int dv_reg;
43 typedef volatile unsigned int * dv_reg_p;
46 * Base register addresses
48 * NOTE: some of these DM6446-specific addresses DO NOT WORK
49 * on other DaVinci chips. Double check them before you try
50 * using the addresses ... or PSC module identifiers, etc.
52 #ifndef CONFIG_SOC_DA8XX
54 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
55 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
56 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
57 #define DAVINCI_UART0_BASE (0x01c20000)
58 #define DAVINCI_UART1_BASE (0x01c20400)
59 #define DAVINCI_I2C_BASE (0x01c21000)
60 #define DAVINCI_TIMER0_BASE (0x01c21400)
61 #define DAVINCI_TIMER1_BASE (0x01c21800)
62 #define DAVINCI_WDOG_BASE (0x01c21c00)
63 #define DAVINCI_PWM0_BASE (0x01c22000)
64 #define DAVINCI_PWM1_BASE (0x01c22400)
65 #define DAVINCI_PWM2_BASE (0x01c22800)
66 #define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
67 #define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
68 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
69 #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
70 #define DAVINCI_ARM_INTC_BASE (0x01c48000)
71 #define DAVINCI_USB_OTG_BASE (0x01c64000)
72 #define DAVINCI_CFC_ATA_BASE (0x01c66000)
73 #define DAVINCI_SPI_BASE (0x01c66800)
74 #define DAVINCI_GPIO_BASE (0x01c67000)
75 #define DAVINCI_VPSS_REGS_BASE (0x01c70000)
76 #if !defined(CONFIG_SOC_DM646X)
77 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
78 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
79 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
80 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
82 #define DAVINCI_DDR_BASE (0x80000000)
84 #ifdef CONFIG_SOC_DM644X
85 #define DAVINCI_UART2_BASE 0x01c20800
86 #define DAVINCI_UHPI_BASE 0x01c67800
87 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
88 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
89 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
90 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
91 #define DAVINCI_IMCOP_BASE 0x01cc0000
92 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
93 #define DAVINCI_VLYNQ_BASE 0x01e01000
94 #define DAVINCI_ASP_BASE 0x01e02000
95 #define DAVINCI_MMC_SD_BASE 0x01e10000
96 #define DAVINCI_MS_BASE 0x01e20000
97 #define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
99 #elif defined(CONFIG_SOC_DM355)
100 #define DAVINCI_MMC_SD1_BASE 0x01e00000
101 #define DAVINCI_ASP0_BASE 0x01e02000
102 #define DAVINCI_ASP1_BASE 0x01e04000
103 #define DAVINCI_UART2_BASE 0x01e06000
104 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
105 #define DAVINCI_MMC_SD0_BASE 0x01e11000
107 #elif defined(CONFIG_SOC_DM365)
108 #define DAVINCI_MMC_SD1_BASE 0x01d00000
109 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
110 #define DAVINCI_MMC_SD0_BASE 0x01d11000
112 #elif defined(CONFIG_SOC_DM646X)
113 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
114 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
115 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
116 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
117 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
121 #else /* CONFIG_SOC_DA8XX */
123 #define DAVINCI_UART0_BASE 0x01c42000
124 #define DAVINCI_UART1_BASE 0x01d0c000
125 #define DAVINCI_UART2_BASE 0x01d0d000
126 #define DAVINCI_I2C0_BASE 0x01c22000
127 #define DAVINCI_I2C1_BASE 0x01e28000
128 #define DAVINCI_TIMER0_BASE 0x01c20000
129 #define DAVINCI_TIMER1_BASE 0x01c21000
130 #define DAVINCI_WDOG_BASE 0x01c21000
131 #define DAVINCI_RTC_BASE 0x01c23000
132 #define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
133 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
134 #define DAVINCI_PSC0_BASE 0x01c10000
135 #define DAVINCI_PSC1_BASE 0x01e27000
136 #define DAVINCI_SPI0_BASE 0x01c41000
137 #define DAVINCI_USB_OTG_BASE 0x01e00000
138 #define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
139 0x01e12000 : 0x01f0e000)
140 #define DAVINCI_GPIO_BASE 0x01e26000
141 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
142 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
143 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
144 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
145 #define DAVINCI_SYSCFG1_BASE 0x01e2c000
146 #define DAVINCI_MMC_SD0_BASE 0x01c40000
147 #define DAVINCI_MMC_SD1_BASE 0x01e1b000
148 #define DAVINCI_TIMER2_BASE 0x01f0c000
149 #define DAVINCI_TIMER3_BASE 0x01f0d000
150 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
151 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
152 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
153 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
154 #define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
155 #define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
156 #define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
157 #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
158 #define DAVINCI_INTC_BASE 0xfffee000
159 #define DAVINCI_BOOTCFG_BASE 0x01c14000
160 #define DAVINCI_L3CBARAM_BASE 0x80000000
161 #define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
162 #define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
163 #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
164 #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
166 #define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
167 #define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
168 #define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
169 #define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
170 #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
171 #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
172 #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
173 #define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
174 #endif /* CONFIG_SOC_DA8XX */
176 /* Power and Sleep Controller (PSC) Domains */
177 #define DAVINCI_GPSC_ARMDOMAIN 0
178 #define DAVINCI_GPSC_DSPDOMAIN 1
180 #ifndef CONFIG_SOC_DA8XX
182 #define DAVINCI_LPSC_VPSSMSTR 0
183 #define DAVINCI_LPSC_VPSSSLV 1
184 #define DAVINCI_LPSC_TPCC 2
185 #define DAVINCI_LPSC_TPTC0 3
186 #define DAVINCI_LPSC_TPTC1 4
187 #define DAVINCI_LPSC_EMAC 5
188 #define DAVINCI_LPSC_EMAC_WRAPPER 6
189 #define DAVINCI_LPSC_MDIO 7
190 #define DAVINCI_LPSC_IEEE1394 8
191 #define DAVINCI_LPSC_USB 9
192 #define DAVINCI_LPSC_ATA 10
193 #define DAVINCI_LPSC_VLYNQ 11
194 #define DAVINCI_LPSC_UHPI 12
195 #define DAVINCI_LPSC_DDR_EMIF 13
196 #define DAVINCI_LPSC_AEMIF 14
197 #define DAVINCI_LPSC_MMC_SD 15
198 #define DAVINCI_LPSC_MEMSTICK 16
199 #define DAVINCI_LPSC_McBSP 17
200 #define DAVINCI_LPSC_I2C 18
201 #define DAVINCI_LPSC_UART0 19
202 #define DAVINCI_LPSC_UART1 20
203 #define DAVINCI_LPSC_UART2 21
204 #define DAVINCI_LPSC_SPI 22
205 #define DAVINCI_LPSC_PWM0 23
206 #define DAVINCI_LPSC_PWM1 24
207 #define DAVINCI_LPSC_PWM2 25
208 #define DAVINCI_LPSC_GPIO 26
209 #define DAVINCI_LPSC_TIMER0 27
210 #define DAVINCI_LPSC_TIMER1 28
211 #define DAVINCI_LPSC_TIMER2 29
212 #define DAVINCI_LPSC_SYSTEM_SUBSYS 30
213 #define DAVINCI_LPSC_ARM 31
214 #define DAVINCI_LPSC_SCR2 32
215 #define DAVINCI_LPSC_SCR3 33
216 #define DAVINCI_LPSC_SCR4 34
217 #define DAVINCI_LPSC_CROSSBAR 35
218 #define DAVINCI_LPSC_CFG27 36
219 #define DAVINCI_LPSC_CFG3 37
220 #define DAVINCI_LPSC_CFG5 38
221 #define DAVINCI_LPSC_GEM 39
222 #define DAVINCI_LPSC_IMCOP 40
224 #define DAVINCI_DM646X_LPSC_EMAC 14
225 #define DAVINCI_DM646X_LPSC_UART0 26
226 #define DAVINCI_DM646X_LPSC_I2C 31
227 #define DAVINCI_DM646X_LPSC_TIMER0 34
229 #else /* CONFIG_SOC_DA8XX */
231 #define DAVINCI_LPSC_TPCC 0
232 #define DAVINCI_LPSC_TPTC0 1
233 #define DAVINCI_LPSC_TPTC1 2
234 #define DAVINCI_LPSC_AEMIF 3
235 #define DAVINCI_LPSC_SPI0 4
236 #define DAVINCI_LPSC_MMC_SD 5
237 #define DAVINCI_LPSC_AINTC 6
238 #define DAVINCI_LPSC_ARM_RAM_ROM 7
239 #define DAVINCI_LPSC_SECCTL_KEYMGR 8
240 #define DAVINCI_LPSC_UART0 9
241 #define DAVINCI_LPSC_SCR0 10
242 #define DAVINCI_LPSC_SCR1 11
243 #define DAVINCI_LPSC_SCR2 12
244 #define DAVINCI_LPSC_DMAX 13
245 #define DAVINCI_LPSC_ARM 14
246 #define DAVINCI_LPSC_GEM 15
248 /* for LPSCs in PSC1, offset from 32 for differentiation */
249 #define DAVINCI_LPSC_PSC1_BASE 32
250 #define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
251 #define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
252 #define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
253 #define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
254 #define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
255 #define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
256 #define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
257 #define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
258 #define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
259 #define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
260 #define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
261 #define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
262 #define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
263 #define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
264 #define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
266 /* DA830-specific peripherals */
267 #define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
268 #define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
269 #define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
270 #define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
271 #define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
272 #define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
274 /* DA850-specific peripherals */
275 #define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
276 #define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
277 #define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
278 #define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
279 #define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
280 #define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
281 #define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
282 #define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
283 #define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
284 #define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
285 #define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
286 #define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
287 #define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
288 #define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
289 #define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
291 #endif /* CONFIG_SOC_DA8XX */
293 void lpsc_on(unsigned int id);
296 void davinci_enable_uart0(void);
297 void davinci_enable_emac(void);
298 void davinci_enable_i2c(void);
299 void davinci_errata_workarounds(void);
301 #ifndef CONFIG_SOC_DA8XX
303 /* Some PSC defines */
304 #define PSC_CHP_SHRTSW (0x01c40038)
305 #define PSC_GBLCTL (0x01c41010)
306 #define PSC_EPCPR (0x01c41070)
307 #define PSC_EPCCR (0x01c41078)
308 #define PSC_PTCMD (0x01c41120)
309 #define PSC_PTSTAT (0x01c41128)
310 #define PSC_PDSTAT (0x01c41200)
311 #define PSC_PDSTAT1 (0x01c41204)
312 #define PSC_PDCTL (0x01c41300)
313 #define PSC_PDCTL1 (0x01c41304)
315 #define PSC_MDCTL_BASE (0x01c41a00)
316 #define PSC_MDSTAT_BASE (0x01c41800)
318 #define VDD3P3V_PWDN (0x01c40048)
319 #define UART0_PWREMU_MGMT (0x01c20030)
321 #define PSC_SILVER_BULLET (0x01c41a20)
323 #else /* CONFIG_SOC_DA8XX */
325 #define PSC_ENABLE 0x3
326 #define PSC_DISABLE 0x2
327 #define PSC_SYNCRESET 0x1
328 #define PSC_SWRSTDISABLE 0x0
330 #define PSC_PSC0_MODULE_ID_CNT 16
331 #define PSC_PSC1_MODULE_ID_CNT 32
333 struct davinci_psc_regs {
342 dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
344 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
347 dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
349 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
354 #define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
355 #define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
357 #endif /* CONFIG_SOC_DA8XX */
359 #define PSC_MDSTAT_STATE 0x3f
361 #ifndef CONFIG_SOC_DA8XX
364 #define VBPR (0x20000020)
366 /* NOTE: system control modules are *highly* chip-specific, both
367 * as to register content (e.g. for muxing) and which registers exist.
369 #define PINMUX0 0x01c40000
370 #define PINMUX1 0x01c40004
371 #define PINMUX2 0x01c40008
372 #define PINMUX3 0x01c4000c
373 #define PINMUX4 0x01c40010
375 #else /* CONFIG_SOC_DA8XX */
377 struct davinci_pllc_regs {
410 #define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
411 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
412 #define DAVINCI_PLLC_DIV_MASK 0x1f
414 #define ASYNC3 get_async3_src()
415 #define PLL1_SYSCLK2 ((1 << 16) | 0x2)
416 #define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
418 enum davinci_clk_ids {
419 DAVINCI_SPI0_CLKID = 2,
420 DAVINCI_UART2_CLKID = 2,
421 DAVINCI_MDIO_CLKID = 4,
422 DAVINCI_ARM_CLKID = 6,
423 DAVINCI_PLLM_CLKID = 0xff,
424 DAVINCI_PLLC_CLKID = 0x100,
425 DAVINCI_AUXCLK_CLKID = 0x101
428 int clk_get(enum davinci_clk_ids id);
431 struct davinci_syscfg_regs {
448 #define davinci_syscfg_regs \
449 ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
451 /* Emulation suspend bits */
452 #define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
453 #define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
454 #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
455 #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
456 #define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
457 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
459 struct davinci_syscfg1_regs {
469 #define davinci_syscfg1_regs \
470 ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
472 #define DDR_SLEW_CMOSEN_BIT 4
474 #define VTP_POWERDWN (1 << 6)
475 #define VTP_LOCK (1 << 7)
476 #define VTP_CLKRZ (1 << 13)
477 #define VTP_READY (1 << 15)
478 #define VTP_IOPWRDWN (1 << 14)
480 /* Interrupt controller */
481 struct davinci_aintc_regs {
494 #define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
496 struct davinci_uart_ctrl_regs {
503 #define DAVINCI_UART_CTRL_BASE 0x28
504 #define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
505 #define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
506 #define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
508 #define davinci_uart0_ctrl_regs \
509 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
510 #define davinci_uart1_ctrl_regs \
511 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
512 #define davinci_uart2_ctrl_regs \
513 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
515 /* UART PWREMU_MGMT definitions */
516 #define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
517 #define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
518 #define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
520 static inline int cpu_is_da830(void)
522 unsigned int jtag_id = REG(JTAG_ID_REG);
523 unsigned short part_no = (jtag_id >> 12) & 0xffff;
525 return ((part_no == 0xb7df) ? 1 : 0);
527 static inline int cpu_is_da850(void)
529 unsigned int jtag_id = REG(JTAG_ID_REG);
530 unsigned short part_no = (jtag_id >> 12) & 0xffff;
532 return ((part_no == 0xb7d1) ? 1 : 0);
535 static inline int get_async3_src(void)
537 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
541 #endif /* CONFIG_SOC_DA8XX */
543 #endif /* __ASM_ARCH_HARDWARE_H */