2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/hardware.h>
11 struct davinci_emif_regs {
26 u_int32_t ddrphyid_rev;
38 u_int32_t nandfecc[4];
40 u_int32_t nand4biteccload;
41 u_int32_t nand4bitecc[4];
42 u_int32_t nanderradd1;
43 u_int32_t nanderradd2;
44 u_int32_t nanderrval1;
45 u_int32_t nanderrval2;
48 #define davinci_emif_regs \
49 ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
51 #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
52 #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
53 #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
54 #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
55 #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
56 #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
57 #define DAVINCI_NANDFCR_CS2NAND (1 << 0)
59 /* Chip Select setup */
60 #define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
61 #define DAVINCI_ABCR_EXT_WAIT (1 << 30)
62 #define DAVINCI_ABCR_WSETUP(n) (n << 26)
63 #define DAVINCI_ABCR_WSTROBE(n) (n << 20)
64 #define DAVINCI_ABCR_WHOLD(n) (n << 17)
65 #define DAVINCI_ABCR_RSETUP(n) (n << 13)
66 #define DAVINCI_ABCR_RSTROBE(n) (n << 7)
67 #define DAVINCI_ABCR_RHOLD(n) (n << 4)
68 #define DAVINCI_ABCR_TA(n) (n << 2)
69 #define DAVINCI_ABCR_ASIZE_16BIT 1
70 #define DAVINCI_ABCR_ASIZE_8BIT 0