2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * ----------------------------------------------------------------------------
10 * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
12 * Copyright (C) 2005 Texas Instruments.
14 * ----------------------------------------------------------------------------
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * ----------------------------------------------------------------------------
32 * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
36 #ifndef _DM644X_EMAC_H_
37 #define _DM644X_EMAC_H_
39 #include <asm/arch/hardware.h>
41 #ifdef CONFIG_SOC_DM365
42 #define EMAC_BASE_ADDR (0x01d07000)
43 #define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
44 #define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
45 #define EMAC_MDIO_BASE_ADDR (0x01d0b000)
46 #define DAVINCI_EMAC_VERSION2
47 #elif defined(CONFIG_SOC_DA8XX)
48 #define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
49 #define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
50 #define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
51 #define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
52 #define DAVINCI_EMAC_VERSION2
54 #define EMAC_BASE_ADDR (0x01c80000)
55 #define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
56 #define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
57 #define EMAC_MDIO_BASE_ADDR (0x01c84000)
60 #ifdef CONFIG_SOC_DM646X
61 #define DAVINCI_EMAC_VERSION2
62 #define DAVINCI_EMAC_GIG_ENABLE
65 #ifdef CONFIG_SOC_DM646X
66 /* MDIO module input frequency */
67 #define EMAC_MDIO_BUS_FREQ 76500000
68 /* MDIO clock output frequency */
69 #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
70 #elif defined(CONFIG_SOC_DM365)
71 /* MDIO module input frequency */
72 #define EMAC_MDIO_BUS_FREQ 121500000
73 /* MDIO clock output frequency */
74 #define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
75 #elif defined(CONFIG_SOC_DA8XX)
76 /* MDIO module input frequency */
77 #define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
78 /* MDIO clock output frequency */
79 #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
81 /* MDIO module input frequency */
82 #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
83 /* MDIO clock output frequency */
84 #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
87 /* PHY mask - set only those phy number bits where phy is/can be connected */
88 #define EMAC_MDIO_PHY_NUM CONFIG_EMAC_MDIO_PHY_NUM
89 #define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM)
91 /* Ethernet Min/Max packet size */
92 #define EMAC_MIN_ETHERNET_PKT_SIZE 60
93 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518
94 #define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
96 /* Number of RX packet buffers
97 * NOTE: Only 1 buffer supported as of now
99 #define EMAC_MAX_RX_BUFFERS 10
102 /***********************************************
103 ******** Internally used macros ***************
104 ***********************************************/
109 /* Each descriptor occupies 4 words, lets start RX desc's at 0 and
110 * reserve space for 64 descriptors max
112 #define EMAC_RX_DESC_BASE 0x0
113 #define EMAC_TX_DESC_BASE 0x1000
115 /* EMAC Teardown value */
116 #define EMAC_TEARDOWN_VALUE 0xfffffffc
118 /* MII Status Register */
119 #define MII_STATUS_REG 1
121 /* Number of statistics registers */
122 #define EMAC_NUM_STATS 36
125 /* EMAC Descriptor */
126 typedef volatile struct _emac_desc
128 u_int32_t next; /* Pointer to next descriptor in chain */
129 u_int8_t *buffer; /* Pointer to data buffer */
130 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
131 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
134 /* CPPI bit positions */
135 #define EMAC_CPPI_SOP_BIT (0x80000000)
136 #define EMAC_CPPI_EOP_BIT (0x40000000)
137 #define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
138 #define EMAC_CPPI_EOQ_BIT (0x10000000)
139 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
140 #define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
142 #define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
144 #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
145 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
146 #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
147 #define EMAC_MACCONTROL_GIGFORCE (1 << 17)
148 #define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
150 #define EMAC_MAC_ADDR_MATCH (1 << 19)
151 #define EMAC_MAC_ADDR_IS_VALID (1 << 20)
153 #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
154 #define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
157 #define MDIO_CONTROL_IDLE (0x80000000)
158 #define MDIO_CONTROL_ENABLE (0x40000000)
159 #define MDIO_CONTROL_FAULT_ENABLE (0x40000)
160 #define MDIO_CONTROL_FAULT (0x80000)
161 #define MDIO_USERACCESS0_GO (0x80000000)
162 #define MDIO_USERACCESS0_WRITE_READ (0x0)
163 #define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
164 #define MDIO_USERACCESS0_ACK (0x20000000)
166 /* Ethernet MAC Registers Structure */
177 dv_reg TXINTSTATMASKED;
179 dv_reg TXINTMASKCLEAR;
183 dv_reg RXINTSTATMASKED;
185 dv_reg RXINTMASKCLEAR;
186 dv_reg MACINTSTATRAW;
187 dv_reg MACINTSTATMASKED;
188 dv_reg MACINTMASKSET;
189 dv_reg MACINTMASKCLEAR;
193 dv_reg RXUNICASTCLEAR;
195 dv_reg RXBUFFEROFFSET;
196 dv_reg RXFILTERLOWTHRESH;
198 dv_reg RX0FLOWTHRESH;
199 dv_reg RX1FLOWTHRESH;
200 dv_reg RX2FLOWTHRESH;
201 dv_reg RX3FLOWTHRESH;
202 dv_reg RX4FLOWTHRESH;
203 dv_reg RX5FLOWTHRESH;
204 dv_reg RX6FLOWTHRESH;
205 dv_reg RX7FLOWTHRESH;
206 dv_reg RX0FREEBUFFER;
207 dv_reg RX1FREEBUFFER;
208 dv_reg RX2FREEBUFFER;
209 dv_reg RX3FREEBUFFER;
210 dv_reg RX4FREEBUFFER;
211 dv_reg RX5FREEBUFFER;
212 dv_reg RX6FREEBUFFER;
213 dv_reg RX7FREEBUFFER;
231 dv_reg RXBCASTFRAMES;
232 dv_reg RXMCASTFRAMES;
233 dv_reg RXPAUSEFRAMES;
235 dv_reg RXALIGNCODEERRORS;
241 dv_reg RXQOSFILTERED;
244 dv_reg TXBCASTFRAMES;
245 dv_reg TXMCASTFRAMES;
246 dv_reg TXPAUSEFRAMES;
251 dv_reg TXEXCESSIVECOLL;
254 dv_reg TXCARRIERSENSE;
260 dv_reg FRAME512T1023;
263 dv_reg RXSOFOVERRUNS;
264 dv_reg RXMOFOVERRUNS;
265 dv_reg RXDMAOVERRUNS;
305 /* EMAC Wrapper Registers Structure */
307 #ifdef DAVINCI_EMAC_VERSION2
323 dv_reg c0rxthreshstat;
327 dv_reg c1rxthreshstat;
331 dv_reg c2rxthreshstat;
342 u_int8_t RSVD0[4100];
348 /* EMAC MDIO Registers Structure */
355 dv_reg LINKINTMASKED;
358 dv_reg USERINTMASKED;
359 dv_reg USERINTMASKSET;
360 dv_reg USERINTMASKCLEAR;
368 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
369 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
374 int (*init)(int phy_addr);
375 int (*is_phy_connected)(int phy_addr);
376 int (*get_link_speed)(int phy_addr);
377 int (*auto_negotiate)(int phy_addr);
380 #define PHY_KSZ8873 (0x00221450)
381 int ksz8873_is_phy_connected(int phy_addr);
382 int ksz8873_get_link_speed(int phy_addr);
383 int ksz8873_init_phy(int phy_addr);
384 int ksz8873_auto_negotiate(int phy_addr);
386 #define PHY_LXT972 (0x001378e2)
387 int lxt972_is_phy_connected(int phy_addr);
388 int lxt972_get_link_speed(int phy_addr);
389 int lxt972_init_phy(int phy_addr);
390 int lxt972_auto_negotiate(int phy_addr);
392 #define PHY_DP83848 (0x20005c90)
393 int dp83848_is_phy_connected(int phy_addr);
394 int dp83848_get_link_speed(int phy_addr);
395 int dp83848_init_phy(int phy_addr);
396 int dp83848_auto_negotiate(int phy_addr);
398 #define PHY_ET1011C (0x282f013)
399 int et1011c_get_link_speed(int phy_addr);
401 #endif /* _DM644X_EMAC_H_ */