2 * Copyright (C) 2013 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __ATMEL_MPDDRC_H__
9 #define __ATMEL_MPDDRC_H__
12 * Only define the needed register in mpddr
13 * If other register needed, will add them later
26 int ddr2_init(const unsigned int ram_address,
27 const struct atmel_mpddr *mpddr);
29 /* Bit field in mode register */
30 #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0
31 #define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1
32 #define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2
33 #define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3
34 #define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4
35 #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5
36 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6
37 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7
39 /* Bit field in configuration register */
40 #define ATMEL_MPDDRC_CR_NC_MASK 0x3
41 #define ATMEL_MPDDRC_CR_NC_COL_9 0x0
42 #define ATMEL_MPDDRC_CR_NC_COL_10 0x1
43 #define ATMEL_MPDDRC_CR_NC_COL_11 0x2
44 #define ATMEL_MPDDRC_CR_NC_COL_12 0x3
45 #define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2)
46 #define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2)
47 #define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2)
48 #define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2)
49 #define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2)
50 #define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4)
51 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4)
52 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4)
53 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4)
54 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4)
55 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4)
56 #define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7)
57 #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8)
58 #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9)
59 #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12)
60 #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17)
61 #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20)
62 #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21)
63 #define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22)
64 #define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23)
66 /* Bit field in timing parameter 0 register */
67 #define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0
68 #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf
69 #define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4
70 #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf
71 #define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8
72 #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf
73 #define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12
74 #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf
75 #define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16
76 #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf
77 #define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20
78 #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf
79 #define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24
80 #define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7
81 #define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27
82 #define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1
83 #define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28
84 #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf
86 /* Bit field in timing parameter 1 register */
87 #define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0
88 #define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f
89 #define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8
90 #define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff
91 #define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16
92 #define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff
93 #define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24
94 #define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf
96 /* Bit field in timing parameter 2 register */
97 #define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0
98 #define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf
99 #define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4
100 #define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf
101 #define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8
102 #define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf
103 #define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12
104 #define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7
105 #define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16
106 #define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf
108 /* Bit field in Memory Device Register */
109 #define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3
110 #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6
111 #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4)
112 #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4)
113 #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4)