2 * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
8 * Parallel I/O Controller (PIO) - System peripherals registers.
9 * Based on AT91RM9200 datasheet revision E.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
21 #define AT91_ASM_PIO_RANGE 0x200
22 #define AT91_ASM_PIOC_ASR \
23 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
24 #define AT91_ASM_PIOC_BSR \
25 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
26 #define AT91_ASM_PIOC_PDR \
27 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
28 #define AT91_ASM_PIOC_PUDR \
29 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
31 #define AT91_ASM_PIOD_PDR \
32 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
33 #define AT91_ASM_PIOD_PUDR \
34 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
35 #define AT91_ASM_PIOD_ASR \
36 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
40 typedef struct at91_port {
41 u32 per; /* 0x00 PIO Enable Register */
42 u32 pdr; /* 0x04 PIO Disable Register */
43 u32 psr; /* 0x08 PIO Status Register */
45 u32 oer; /* 0x10 Output Enable Register */
46 u32 odr; /* 0x14 Output Disable Registerr */
47 u32 osr; /* 0x18 Output Status Register */
49 u32 ifer; /* 0x20 Input Filter Enable Register */
50 u32 ifdr; /* 0x24 Input Filter Disable Register */
51 u32 ifsr; /* 0x28 Input Filter Status Register */
53 u32 sodr; /* 0x30 Set Output Data Register */
54 u32 codr; /* 0x34 Clear Output Data Register */
55 u32 odsr; /* 0x38 Output Data Status Register */
56 u32 pdsr; /* 0x3C Pin Data Status Register */
57 u32 ier; /* 0x40 Interrupt Enable Register */
58 u32 idr; /* 0x44 Interrupt Disable Register */
59 u32 imr; /* 0x48 Interrupt Mask Register */
60 u32 isr; /* 0x4C Interrupt Status Register */
61 u32 mder; /* 0x50 Multi-driver Enable Register */
62 u32 mddr; /* 0x54 Multi-driver Disable Register */
63 u32 mdsr; /* 0x58 Multi-driver Status Register */
65 u32 pudr; /* 0x60 Pull-up Disable Register */
66 u32 puer; /* 0x64 Pull-up Enable Register */
67 u32 pusr; /* 0x68 Pad Pull-up Status Register */
69 #if defined(CPU_HAS_PIO3)
70 u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
71 u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
73 u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
74 u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
75 u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
76 u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
77 u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
78 u32 ppder; /* 0x94 Pad Pull-down Enable Register */
79 u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
82 u32 asr; /* 0x70 Select A Register */
83 u32 bsr; /* 0x74 Select B Register */
84 u32 absr; /* 0x78 AB Select Status Register */
85 u32 reserved5[9]; /* */
87 u32 ower; /* 0xA0 Output Write Enable Register */
88 u32 owdr; /* 0xA4 Output Write Disable Register */
89 u32 owsr; /* OxA8 Output Write Status Register */
90 #if defined(CPU_HAS_PIO3)
92 u32 aimer; /* 0xB0 Additional INT Modes Enable Register */
93 u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */
94 u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */
96 u32 esr; /* 0xC0 Edge Select Register */
97 u32 lsr; /* 0xC4 Level Select Register */
98 u32 elsr; /* 0xC8 Edge/Level Status Register */
99 u32 reserved9; /* 0xCC */
100 u32 fellsr; /* 0xD0 Falling /Low Level Select Register */
101 u32 rehlsr; /* 0xD4 Rising /High Level Select Register */
102 u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
103 u32 reserved10; /* */
104 u32 locksr; /* 0xE0 Lock Status */
105 u32 wpmr; /* 0xE4 Write Protect Mode Register */
106 u32 wpsr; /* 0xE8 Write Protect Status Register */
107 u32 reserved11[5]; /* */
108 u32 schmitt; /* 0x100 Schmitt Trigger Register */
115 typedef union at91_pio {
120 #if (ATMEL_PIO_PORTS > 3)
123 #if (ATMEL_PIO_PORTS > 4)
127 at91_port_t port[ATMEL_PIO_PORTS];
130 #ifdef CONFIG_AT91_GPIO
131 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
132 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
133 #if defined(CPU_HAS_PIO3)
134 int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
135 int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
136 int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
137 int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
138 int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
140 int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
141 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
142 int at91_set_pio_output(unsigned port, unsigned pin, int value);
143 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
144 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
145 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
146 int at91_set_pio_value(unsigned port, unsigned pin, int value);
147 int at91_get_pio_value(unsigned port, unsigned pin);
151 #define AT91_PIO_PORTA 0x0
152 #define AT91_PIO_PORTB 0x1
153 #define AT91_PIO_PORTC 0x2
154 #define AT91_PIO_PORTD 0x3
155 #define AT91_PIO_PORTE 0x4
157 #ifdef CONFIG_AT91_LEGACY
159 #define PIO_PER 0x00 /* Enable Register */
160 #define PIO_PDR 0x04 /* Disable Register */
161 #define PIO_PSR 0x08 /* Status Register */
162 #define PIO_OER 0x10 /* Output Enable Register */
163 #define PIO_ODR 0x14 /* Output Disable Register */
164 #define PIO_OSR 0x18 /* Output Status Register */
165 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
166 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
167 #define PIO_IFSR 0x28 /* Glitch Input Filter Status */
168 #define PIO_SODR 0x30 /* Set Output Data Register */
169 #define PIO_CODR 0x34 /* Clear Output Data Register */
170 #define PIO_ODSR 0x38 /* Output Data Status Register */
171 #define PIO_PDSR 0x3c /* Pin Data Status Register */
172 #define PIO_IER 0x40 /* Interrupt Enable Register */
173 #define PIO_IDR 0x44 /* Interrupt Disable Register */
174 #define PIO_IMR 0x48 /* Interrupt Mask Register */
175 #define PIO_ISR 0x4c /* Interrupt Status Register */
176 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
177 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
178 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
179 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
180 #define PIO_PUER 0x64 /* Pull-up Enable Register */
181 #define PIO_PUSR 0x68 /* Pull-up Status Register */
182 #define PIO_ASR 0x70 /* Peripheral A Select Register */
183 #define PIO_BSR 0x74 /* Peripheral B Select Register */
184 #define PIO_ABSR 0x78 /* AB Status Register */
185 #define PIO_OWER 0xa0 /* Output Write Enable Register */
186 #define PIO_OWDR 0xa4 /* Output Write Disable Register */
187 #define PIO_OWSR 0xa8 /* Output Write Status Register */