2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #define AT91_ASM_MC_EBI_CSA (AT91_MC_BASE + 0x60)
27 #define AT91_ASM_MC_EBI_CFG (AT91_MC_BASE + 0x64)
28 #define AT91_ASM_MC_SMC_CSR0 (AT91_MC_BASE + 0x70)
29 #define AT91_ASM_MC_SDRAMC_MR (AT91_MC_BASE + 0x90)
30 #define AT91_ASM_MC_SDRAMC_TR (AT91_MC_BASE + 0x94)
31 #define AT91_ASM_MC_SDRAMC_CR (AT91_MC_BASE + 0x98)
35 typedef struct at91_ebi {
36 u32 csa; /* 0x00 Chip Select Assignment Register */
37 u32 cfgr; /* 0x04 Configuration Register */
39 } __attribute__ ((packed)) at91_ebi_t;
41 #define AT91_EBI_CSA_CS0A 0x0001
42 #define AT91_EBI_CSA_CS1A 0x0002
44 #define AT91_EBI_CSA_CS3A 0x0008
45 #define AT91_EBI_CSA_CS4A 0x0010
47 typedef struct at91_sdramc {
48 u32 mr; /* 0x00 SDRAMC Mode Register */
49 u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
50 u32 cr; /* 0x08 SDRAMC Configuration Register */
51 u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
52 u32 lpr; /* 0x10 SDRAMC Low Power Register */
53 u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
54 u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
55 u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
56 u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
58 } __attribute__ ((packed)) at91_sdramc_t;
60 typedef struct at91_smc {
61 u32 csr[8]; /* 0x00 SDRAMC Mode Register */
62 } __attribute__ ((packed)) at91_smc_t;
64 #define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
65 #define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24)
66 #define AT91_SMC_CSR_ACSS_STANDARD 0x00000000
67 #define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000
68 #define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000
69 #define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000
70 #define AT91_SMC_CSR_DRP 0x00008000
71 #define AT91_SMC_CSR_DBW_8 0x00004000
72 #define AT91_SMC_CSR_DBW_16 0x00002000
73 #define AT91_SMC_CSR_BAT_8 0x00000000
74 #define AT91_SMC_CSR_BAT_16 0x00001000
75 #define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8)
76 #define AT91_SMC_CSR_WSEN 0x00000080
77 #define AT91_SMC_CSR_NWS(x) (x & 0x7F)
79 typedef struct at91_bfc {
80 u32 mr; /* 0x00 SDRAMC Mode Register */
81 } __attribute__ ((packed)) at91_bfc_t;
83 typedef struct at91_mc {
84 u32 rcr; /* 0x00 MC Remap Control Register */
85 u32 asr; /* 0x04 MC Abort Status Register */
86 u32 aasr; /* 0x08 MC Abort Address Status Reg */
87 u32 mpr; /* 0x0C MC Master Priority Register */
88 u32 reserved1[20]; /* 0x10-0x5C */
89 at91_ebi_t ebi; /* 0x60 - 0x6C EBI */
90 at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */
91 at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */
92 at91_bfc_t bfc; /* 0xC0 BFC User Interface */
94 } __attribute__ ((packed)) at91_mc_t;