2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
29 #define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C)
30 #elif defined(CONFIG_AT91SAM9261)
31 #define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30)
32 #elif defined(CONFIG_AT91SAM9263)
33 #define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120)
34 #elif defined(CONFIG_AT91SAM9G45)
35 #define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128)
37 #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
40 #define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE
43 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
44 #define AT91_MATRIX_MASTERS 6
45 #define AT91_MATRIX_SLAVES 5
46 #elif defined(CONFIG_AT91SAM9261)
47 #define AT91_MATRIX_MASTERS 1
48 #define AT91_MATRIX_SLAVES 5
49 #elif defined(CONFIG_AT91SAM9263)
50 #define AT91_MATRIX_MASTERS 9
51 #define AT91_MATRIX_SLAVES 7
52 #elif defined(CONFIG_AT91SAM9G45)
53 #define AT91_MATRIX_MASTERS 11
54 #define AT91_MATRIX_SLAVES 8
56 #error CPU not supported. Please update at91_matrix.h
59 typedef struct at91_priority {
64 typedef struct at91_matrix {
65 u32 mcfg[AT91_MATRIX_MASTERS];
66 #if defined(CONFIG_AT91SAM9261)
67 u32 scfg[AT91_MATRIX_SLAVES];
75 u32 reserve1[16 - AT91_MATRIX_MASTERS];
76 u32 scfg[AT91_MATRIX_SLAVES];
77 u32 reserve2[16 - AT91_MATRIX_SLAVES];
78 at91_priority_t pr[AT91_MATRIX_SLAVES];
79 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
80 u32 mrcr; /* 0x100 Master Remap Control */
82 #if defined(CONFIG_AT91SAM9G45)
83 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
84 u32 womr; /* 0x1E4 Write Protect Mode */
85 u32 wpsr; /* 0x1E8 Write Protect Status */
87 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
91 #elif defined(CONFIG_AT91SAM9263)
103 #endif /* __ASSEMBLY__ */
105 #define AT91_MATRIX_CSA_DBPUC 0x00000100
106 #define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
107 #define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000
109 #define AT91_MATRIX_CSA_EBI_CS1A 0x00000002
110 #define AT91_MATRIX_CSA_EBI_CS3A 0x00000008
111 #define AT91_MATRIX_CSA_EBI_CS4A 0x00000010
112 #define AT91_MATRIX_CSA_EBI_CS5A 0x00000020
114 #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
116 #if defined CONFIG_AT91SAM9261
117 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
118 #define AT91_MATRIX_MCFG_RCB0 (1 << 0)
119 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
120 #define AT91_MATRIX_MCFG_RCB1 (1 << 1)
123 /* Undefined Length Burst Type */
124 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
125 defined(CONFIG_AT91SAM9G45)
126 #define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
127 #define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
128 #define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
129 #define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
130 #define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
132 #if defined(CONFIG_AT91SAM9G45)
133 #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
134 #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
135 #define AT91_MATRIX_MCFG_ULBT_128 0x00000007
138 /* Default Master Type */
139 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000
140 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000
141 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
143 /* Fixed Index of Default Master */
144 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
145 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
146 #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
147 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
150 /* Maximum Number of Allowed Cycles for a Burst */
151 #if defined(CONFIG_AT91SAM9G45)
152 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
153 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
154 defined(CONFIG_AT91SAM9263)
155 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
158 /* Arbitration Type */
159 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
160 #define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000
161 #define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000
164 /* Master Remap Control Register */
165 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
166 defined(CONFIG_AT91SAM9G45)
167 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
168 #define AT91_MATRIX_MRCR_RCB0 (1 << 0)
169 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
170 #define AT91_MATRIX_MRCR_RCB1 (1 << 1)
172 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
173 #define AT91_MATRIX_MRCR_RCB2 0x00000004
174 #define AT91_MATRIX_MRCR_RCB3 0x00000008
175 #define AT91_MATRIX_MRCR_RCB4 0x00000010
176 #define AT91_MATRIX_MRCR_RCB5 0x00000020
177 #define AT91_MATRIX_MRCR_RCB6 0x00000040
178 #define AT91_MATRIX_MRCR_RCB7 0x00000080
179 #define AT91_MATRIX_MRCR_RCB8 0x00000100
181 #if defined(CONFIG_AT91SAM9G45)
182 #define AT91_MATRIX_MRCR_RCB9 0x00000200
183 #define AT91_MATRIX_MRCR_RCB10 0x00000400
184 #define AT91_MATRIX_MRCR_RCB11 0x00000800
187 /* TCM Configuration Register */
188 #if defined(CONFIG_AT91SAM9G45)
189 /* Size of ITCM enabled memory block */
190 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
191 #define AT91_MATRIX_TCMR_ITCM_32 0x00000040
192 /* Size of DTCM enabled memory block */
193 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
194 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
195 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070
196 /* Wait state TCM register */
197 #define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000
198 #define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800
200 #if defined(CONFIG_AT91SAM9263)
201 /* Size of ITCM enabled memory block */
202 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
203 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005
204 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006
205 /* Size of DTCM enabled memory block */
206 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
207 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050
208 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
210 #if defined(CONFIG_AT91SAM9261)
211 /* Size of ITCM enabled memory block */
212 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
213 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005
214 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006
215 #define AT91_MATRIX_TCMR_ITCM_64 0x00000007
216 /* Size of DTCM enabled memory block */
217 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
218 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050
219 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
220 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070
223 #if defined(CONFIG_AT91SAM9G45)
224 /* Video Mode Configuration Register */
225 #define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
226 #define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
227 /* Write Protect Mode Register */
228 #define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000
229 #define AT91_MATRIX_WPMR_WP_WPEN 0x00000001
230 #define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */
231 /* Write Protect Status Register */
232 #define AT91_MATRIX_WPSR_NO_WPV 0x00000000
233 #define AT91_MATRIX_WPSR_WPV 0x00000001
234 #define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */
237 /* USB Pad Pull-Up Control Register */
238 #if defined(CONFIG_AT91SAM9261)
239 #define AT91_MATRIX_USBPUCR_PUON 0x40000000
242 #define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/
243 #define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/
244 #define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/
245 #define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/
246 #define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/
247 #define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/
248 #define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/
249 #define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/
250 #define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */
251 #define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */
252 #define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */